Tan Lip-Bu Sets the Tone

In his inaugural keynote as Intel's CEO, Tan Lip-Bu emphasized a customer-centric approach, urging partners to provide candid feedback to drive continuous improvement. Tan's message was clear that Intel is fully committed to its foundry business and is taking decisive steps to earn the trust of its customers.

More important today is to listen to our customer. I would love your feedback so that we can better serve you.

Now I've been the CEO for about 5 weeks now. And then some of the people are asking me, since I joined Intel, Lip-Bu, "are you committed to the foundry?" The answer is yes. I'm so excited today to share with you. I'm committed to make the Intel Foundry successful, and I know there are areas we need to improve. I'm determined to strengthen our road map and our partnership and our execution going forward. As we drive this improvement, we see a lot of opportunity ahead of us.

For once, we might have an Intel CEO who truly understands what it takes to succeed in the foundry business.

I really embrace the industry standard IP and EDA so that we can really help you and serve you better. And this is truly a service business, and that is built on the foundational principle of trust. And you have to be patient to earn your trust. And then we have to really driving some of the technology to make sure that the yield and performance and reliability meet your requirement.

We will be guided by the Voice of the Customer, all of you, and we'll act on your feedback. We are humble in that approach, as you can tell, because we know your success is matter the most than anything else. And we work every day to earn your trust.

Source: Intel

TSMC has always emphasized trust as a core value of the company given that trust is the bedrock of the foundry business. Unlike IDMs, foundries don’t sell end products. They sell reliability, confidentiality and execution. When companies like Apple and NVIDIA hand over their most sensitive chip designs to a foundry, they require assurance that TSMC would never compete with them and to deliver as promised. Integrity and trust go hand in hand.

Source: TSMC

Seeing Intel labels trust as a foundational principle is both refreshing and assuring. Trust is not about exaggerating your future technology roadmap potential, but to provide a reliable roadmap that customers can depend on to deliver their new products on time. Of course, Intel’s challenge is unique as it’s both a foundry and an IDM competitor. Whether customers believe Intel can replicate the trust TSMC earned over 30 years will be central to its foundry ambitions. Tan Lip-Bu also understands that foundry is a service business. The mindset change is important as foundry is much more than having superior technology.

In another sign of Tan Lip-Bu strong interpersonal relationship, CEOs of all 3 major EDA tools Sassine Ghazi (Synopsys), Anirudh Devgan (Cadence) and Mike Ellow (Siemens EDA) went on stage.

Intel shared that they had invested a total of $90 billion on property, plant, equipment and R&D. For comparison, TSMC had spent a total of $150 billion in the same period which is more than 50% higher than Intel. This year, Intel will spend a gross capex of $18 billion (net capex of $8 to $11 billion) while TSMC will spend a total capex of $38 to 42 billion. Leverage, lack of scale, low utilization rate and a core business under threat remain impediment as Intel embarks on this capital-intensive business. TSMC is expected to grow its revenue by more than 25% to $110 billion this year, while Intel’s revenue is expected to decline by mid-single digit to $50 billion.

Source: Intel

Intel Foundry Process Roadmap

The main highlight of the process roadmap is 18A, 18A-P, 14A and 14A-E

Source: Intel

Intel 18A Is Ramping

Intel’s 18A will be the 1^st node to feature two key technology innovations in RibbonFET, Intel’s gate-all-around transistor architecture, and PowerVia, their take on backside power delivery. 18A will boast a density improvement of 30%, performance/watt improvement of 15% relative to Intel 3.

Back in 2021, Pat Gelsinger came out with the target to achieve 5 nodes in 4 years. Intel is on track to meet the goal as 18A is in risk production with volume ramp expected later this year. However, real volume ramp of Panther Lake (built on 18A) will be in 2026.

Defect density continues to improve in Q4 2024 and Q1 2025. Intel had previously revealed that their D0 (defect density) is 0.4 for 18A in September 2024. Intel’s D0 is likely to be somewhere between 0.2 to 0.3 right now. While this is higher than TSMC’s D0 of <0.2 for N2, Intel is on track for mass production of 18A.

Source: TSMC Technology Symposium 2025

Introduced during the event, Intel 18A-P is a newly announced enhancement of Intel’s 18A process node. Intel’s 18A-P is a performance-enhanced variant of 18A optimized for customers demanding better performance.

With mass production in 2026, 18A-P has design rule compatibility with 18A and offers an 8% improvement in performance. Because of the design rule compatibility, most of the IP will be able to port over from 18A to 18A-P seamlessly. Again, this is like what TSMC has always done in introducing application specific derivatives nodes that are more suitable for clients. Design rule is usually compatible between derivatives nodes. N3E was introduced at a lower cost to replace N3B and now TSMC offers N3X, N3A and N3C.

With the better performance and more mature IP, 18A-P will become more competitive in the foundry market.

Source: TSMC Technology Symposium 2025

Another variant, 18A-PT, has also been introduced with the main feature being the addition of TSV. This will be more suitable for AI applications where 18A-PT can be used as a base die for further integration with HBM.

Source: Intel

Intel 14A: High-NA EUV Adoption Remains Uncertain

Intel also commented on 14A which is set for risk production in Oregon in 2027. 14A is expected to offer a 15-20% improvement in performance/ watt, 30% density gain, and 25-35% power reduction compared to 18A. At the same time, 14A will feature their 2^nd generation of RibbonFET and backside power delivery.

While some might claim that Intel is 1 year ahead of TSMC with 14A, 2028 is likely to be the year of mass production for 14A as 2027 is the year of risk production. We have seen how 18A has started risk production, but actual mass production tracks closely with TSMC.

Source: TSMC Technology Symposium 2025

For the 2^nd generation of backside power delivery, Intel has called it PowerDirect. PowerDirect is a more advanced form of backside power delivery network as it involves direct backside contact to the source/drain. This is like TSMC’s adoption of Super Power Rail for A16 in 2026. For 18A, Intel had adopted the Power Via method which is an intermediate solution between Buried Power Rail and Direct Contact.

Source: Applied Material

With regards to High-NA EUV, Intel made a comment that implies it is evaluating the cost effectiveness of introducing the new technology at 14A. Cost effectiveness is an important consideration for foundry. While High-NA EUV can reduce the number of process steps and simplify the process, the additional cost is still a hurdle for end customers. This is why I continue to believe that High-NA EUV adoption by TSMC will be more likely in 2030.

Intel’s roadmap still represents a few years delay in High-NA EUV adoption as Intel under Pat Gelsinger had previously mentioned about High-NA EUV involvement in production starting in 2025. Pat Gelsinger was too aggressive on being the 1^st to High-NA EUV when we have seen previous multi-years delay for Low-NA EUV adoption. High-NA EUV alone is not going to help Intel wins the foundry market.

Source: ASML and Intel joint announcement

This is a change in tone regarding to the adoption of High-NA EUV for 14A. Regardless, customers can proceed with their 14A design as it does not matter whether High-NA EUV will be adopted or not.

One of the differentiating factors on 14A is High-NA EUV tool. In Oregon, we have landed our second High-NA EUV tool. In fact, this tool came up much faster compared to our first one, and we are working in great collaboration with ASML. The tool is performing well to its expectations. I want to make 2 points for the audience today.

The first one is Intel still has the option to have either a low-NA or a High-NA solution on our 14A technology, and it's design rule compatible. There will be no impact to the customers depending on the path that we choose.

Second, the High-NA EUV is performing to the expectations, and we will introduce it at the right time. We already have data on 18A as well as 14A that shows yield parity between our low-NA-based solution and a High-NA-based solution. So we are continuing to make progress on the technology front and ensuring that we have the right options available for us to make sure the solution we deliver to our customers has the lowest risk and the best reward in terms of the decisions we make.

Advanced Packaging

Intel EMIB (Embedded Multi-die Interconnect Bridge) is a 2.5D advanced packaging technology that enables high-bandwidth, low-latency communication between multiple chiplets on a single substrate. Instead of using silicon interposer like CoWoS, it uses silicon bridge to connect the dies.

Intel announced the introduction of TSV (Through-Silicon Vias) capability for their EMIB technology with the EMIB-T solution. This is a more scalable solution, especially if AI clients wanted to add more HBM content.

Source: Intel

The other key advanced packaging solution of Intel is Foveros. Intel has introduced 2 new solutions, Foveros-B and Foveros-R, that will be production ready in 2027.

• Foveros-S uses silicon interposer and is in use for PC application

• Foveros-R uses RDL (redistribution layer) as a cost sensitive solution

• Foveros-B combines both RDL and silicon bridge for complex designs

Source: Intel

This is similar with TSMC’s 3 versions of CoWoS

• CoWoS-S uses silicon interposer and is adopted by NVIDIA’s Hopper

• CoWoS-R uses RDL (redistribution layer) as the interposer and is adopted by AWS’s Tranium

• CoWoS-L uses an interposer with a Local Silicon Interconnect (LSI) chip for die-to-die interconnect and RDL layers for power and signal delivery. This is adopted by NVIDIA’s Blackwell

Source: TSMC

The next advancement will be Intel’s Foveros Direct, which is their 3D stacking solution. Through die-to-wafer hybrid bonding, dies are bonded to the substrate wafer using copper-to-copper interconnect. Bond pitch smaller than 10 um can be achieved as compared to sub-25 um for Foveros 2.5D.

Source: Intel

Advanced packaging is an area that Intel is obviously still lagging TSMC by a few years. While TSMC has started to implement CoWoS-L for NVIDIA’s Blackwell in 2024, Intel’s Foveros-B will only be ready in 2027. In the area of hybrid bonding, TSMC’s SoIC has been in production since 2022 with pitch size as small as 6um in 2025.

Source: TSMC

Strengthening the Ecosystem

Intel also announced the formation of the Intel Foundry Chiplet Alliance and Value Chain Alliance, aiming to foster collaboration across the semiconductor ecosystem. Key EDA partners like Synopsys, Cadence and Siemens are working closely with Intel to develop certified design flows and IP for the 18A and 14A nodes. These collaborations are essential for ensuring a robust design environment for customers.

Source: Intel

It’s a smart move as Intel knows it can’t go it alone. And it’s borrowing a page from TSMC’s playbook by trying to create a collaborative ecosystem that makes it easier for customers to bring designs to tape-out. There is still lots for Intel to do to catch up with TSMC’s well known Open Innovation Platform.

Source: TSMC

Conclusion

If former CEO Pat Gelsinger was focused on getting Intel technologically ready for the foundry race, Tan Lip-Bu is now mastering the intricacies of the foundry business. Intel’s new CEO understands what it takes to succeed as a foundry and he’s beginning to speak the language of TSMC. Intel Foundry is emerging as a player to watch in the semiconductor foundry industry, even if it still faces clear disadvantages across several fronts.

You can also check out my recent article on TSMC 2025 Technology Symposium.

All slides below are from TSMC Technology Symposium. Here are the key takeaways that matter for both investors and industry watchers.

Semiconductor Market Outlook

According to TSMC, they continue to expect the global semiconductor market to grow by 10% in 2025. Similar to last year, Dr Kevin Zhang affirmed that the global semiconductor market will grow to $1 trillion by 2030. HPC/AI will account for 45%, followed by 25% for smartphone, 15% for automotive, 5% for IoT and 5% for others. Based on 2024 global semiconductor sales of $621 billion, this implies an 8.1% CAGR in the global semiconductor market from 2024 to 2030. 8.1% CAGR is the fastest the semiconductor market has grown since 2000.

The key driver behind the strong growth outlook is driven primarily by HPC/AI application. TSMC expects HPC/AI to be a $450 billion market by 2030. In the FY 2024 results call, CEO C.C. Wei believed that their revenue growth from AI accelerators will approach mid-40% CAGR from 2024 to 2029. This is after a 12x increase in wafer demand for AI accelerators from 2021 to 2025.

Currently, all AI customers (other than the Chinese) are working with TSMC on GPU and ASICs. Majority of AI accelerators demand is on 3nm and 5nm, using TSMC’s advanced packaging technology such as CoWoS and SoIC. In the chart below, we can see the scaling of training compute achieved by NVIDIA through leveraging the latest semiconductor technology.

The other major growth driver identified by TSMC is the automotive application which will become a $150 billion market by 2030. While the automotive market remains soft, silicon content is growing rapidly. Rising intelligence in automotive application and higher EV penetration is a boon for the automotive semiconductor market. A lot more sensors and computing power will be needed as cars are moving towards L3 to L5. Compute is also being centralized compared to the MCU dominant setup in traditional cars. Software defined vehicle is enabled by silicon defined vehicle. Use of 3nm for automotive computing and 12nm for MCU is quite a surprising development given the current process technology node used by automotive application.

Smartphone is a stable market given unit shipment has peaked in 2016. Content growth will be the key driver as Apple, Qualcomm and MediaTek continue to migrate to the next leading-edge node. AI smartphone could drive semiconductor content in the near-term, but we will have to wait for 6G in 2030 for a big jump in smartphone semiconductor content. For Wi-Fi, 6/7nm is required to achieve the latest technology of Wi-Fi 7. Image sensor is migrating from 28nm to 12nm, while RF is also migrating to 5/6nm

Both VR and Humanoid robot are new growth driver for global semiconductor market in the future. Many different type of semiconductors are needed to enable Humanoid such as sensor, PMIC, MCU, AP and connectivity. For VR to take off, semiconductor is required to drive 10x improvement in power, cost and form factor.

TSMC Technology Roadmap

Nothing surprising on TSMC’s roadmap with their dedication to small improvement in process technology on an annual cadence. N2 will start to ramp in 2025, followed by N2P and A16 in 2026. A16 is a version of N2 that will be equipped with Super Power Rail.

Similar to what TSMC has always done, they continue to improve on existing nodes and offer derivatives node that is more suitable for clients. TSMC has come up with N3X for client CPU, N3A for automotive and N3C for value product. Apple could be using N3C for its cheaper iPhone in the future. N3 has done really well for TSMC with revenue growth of more than 300% in 2024.

N2, which will adopt the new Gate-All-Around FET architecture, is set to ramp in 2H 2025. N2 will remain the industry leading process node, ahead of Intel’s 18A.

A16, which was introduced last year, will feature Super Power Rail. Super Power Rail is TSMC’s version of Backside Power Delivery (BPD) and is the hardest version of BPD. SPR is most suitable for AI/HPC product with high power requirement. OpenAI is rumored to be one of the early customers of A16 when it ramps in 2H 2026.

The number of new tape-out for N2 will grow a shocking 4x compared to N5 in the 2nd year. In addition to TSMC’s process leadership in N2, AI demand is likely the reason for the high number of tape-out. Google, Amazon, OpenAI, Meta and Microsoft should be looking at N2 node in 2027/28 to get a leg-up over NVIDIA. N2 is a very successful process node as TSMC has been in N3.

At the symposium, TSMC also introduced A14 as the next node that will enter mass production in 2028. This process builds on its nanosheet foundation and promises 10–15% performance gains and 25–30% power savings over N2. The logic density gain, speed improvement and power reduction of 14A are impressive although this is 3 years after the ramp of N2. However, the company will not include backside power delivery at A14. Instead, SPR will be offered as an option in 2029, a decision that diverges from Intel’s more aggressive adoption.

On High-NA EUV, it is unlikely that TSMC will adopt it for A14 due to cost and technology maturity issue. The likely timeline for TSMC to introduce High-NA EUV will be A10 node in 2030/31. However, A14 will see logic pitch shrink, so we are likely to see higher usage of multi-patterning with Low-NA EUV.

Comparing against N3E which was launched in 2H 2023, we can see that Super Power Rail is a great boost for TSMC’s A16 despite its higher cost.

Looking beyond A14, TSMC is already doing their research on future transistors innovation. While Moore’s Law has slowed, it is by no means dead. After GAA, we still have complementary FET (CFET) and High-NA to push the PPA further. The CFET architecture will stack both the n-type and p-type transistors on top of each other. ALD and etching providers will benefit in the transition to CFET architecture. Beyond CFET, TSMC is researching into future materials such as 2D transition metal dichalcogenides (TMD) and carbon nanotube (CNT).

Advanced Packaging Roadmap

Given a slowing Moore’s Law, advanced packaging is increasingly important to achieve further scaling. CoWoS (Chip on Wafer on Substrate) has become such an important term for investors looking at NVIDIA and AI demand in 2024. InFO is one of the key reasons why Apple has sole-sourced at TSMC in the last 10 years. TSMC’s head start in advanced packaging is becoming a barrier of entry for any competitors in addition to its front-end process leadership.

The company’s CoWoS platform continues to scale and TSMC expects to produce interposers up to 5.5x reticle size in 2026 and 9.5x reticle size in 2027. This will be able to integrate 12 HBM stacks alongside 4 AI accelerators. Rubin Ultra in 2027 is likely the 1st customer for this large package. Given that the package is now 9.5x reticle size, TSMC has also started to explore panel-level packaging solution to improve the yield rate.

Source: Data Center Dynamics

TSMC’s SoIC (System on Integrated Chips) platform will support 6um face-to-face hybrid bonding in 2025 and aims to enable A14-on-N2 chip stacking by 2029. The trajectory implies a 20x increase in I/O density in 2029 compared to the first SoIC generation. The growth of SoIC is important for BE Semiconductor investors as it will drive the adoption of hybrid bonder. AMD and Apple will use SoIC at N2 for their HPC application.

TSMC also introduces the SoW-X (System on Wafer) architecture, where wafer scale integration is achieved with CoWoS. The SoW-X platform promises over 40x the computing power of the current CoWoS package used by Blackwell and is slated for production by 2027. Unlike the current SoW-P platform which follows the chip-first approach, SoW-X will be using the chip-last approach. Companies such as Cerabras and Tesla’s Dojo have keen interests in SoW.

These architectural innovations are underpinned by a clear thesis that future performance scaling will come from advanced packaging. This is a distinct paradigm shift, and one that TSMC is leading with R&D, volume production and roadmaps. In addition, TSMC will also be introducing Co-Packaged Optics (CPO) to improve power efficiency and reduce latency of networking communication. Using photon in CPO is more energy efficient rather than electron in the current networking setup. Both Broadcom and NVIDIA are likely early adopters of CPO. TSMC is also seeking to introduce integrated power delivery in CoWoS for better power delivery density for AI application.

Source: Broadcom

Manufacturing Excellence

Dr. Cliff Hou, Deputy Co-COO and Chief Information Security Officer of TSMC, also presented on manufacturing excellence.

Defect density (D0) refers to the number of manufacturing defects found in a given area of a semiconductor wafer, typically measured in defects per centimeter square (defect / cm2). Lower defect density translates to higher yield and cost efficiency as there is higher proportion of usable chips per wafer. The trend of bigger die size also makes defect density more important as bigger die is more affected by higher defect density.

It was very impressive to hear that TSMC’s N2 defect density is better than N3 and N5 2 quarters before mass production. N2 defect density improvement is faster despite the move to the new GAA architecture.

Referencing the data released at the 2020 Technology Symposium, 5nm D0 is approximately 0.2/cm2. This put N2 D0 at less than 0.2/cm2. For reference, Intel said their defect density for 18A is 0.4 back in September 2024.

Source: TSMC Technology Symposium 2020, anandtech

Conclusion

The symposium offered not just a roadmap, but a masterclass in execution. TSMC’s measured approach to node migration reflects a foundry business driven by engineering discipline over marketing hype. Customers are not after the most fancy nodes, but wants a reliable node migration that will not lead to delay in their roadmap.

The heavy emphasis on advanced packaging innovation and leadership shows how TSMC is ahead of its peers in shaping the future of semiconductor innovation.

The boom bust cycle is baked into semiconductor and it’s what makes the industry so beautiful, brutal and never boring. Cycle has been around since the industry existed more than 70 years ago and a downcycle occurs every 3 to 4 years. What makes cycle different for the semiconductor industry is that believer of Moore’s Law knows the industry will always grow to new height. Yes, the semiconductor industry has weathered over 15 downcycles, yet it remains firmly on track to hit $1 trillion in revenue by 2030.

Source: TSMC

Source: World Semiconductor Trade Statistics

There are 2 different drivers of semiconductor downcycle, but they are inherently a mismatch of demand and supply. Supply is inelastic, while demand fluctuates a lot more.

The first is a capacity cycle where fabs have to make investment decision a few years ahead of mass production. During boom period, strong demand gives fab the confidence to invest for the long term structural growth drivers of the industry. Everybody makes the same decision and starts to regret the situation of overcapacity when their capacity come online at the same time. Capacity cycle is a lot less common post GFC given the high level of consolidation in the industry. It still happens for more fragmented segments such as analog (TI), power discrete and SiC substrate.

The second driver is the inventory cycle, which occurs more frequently than the capacity cycle. This is also known as the bullwhip effect, where small changes in end demand can lead to increasingly amplified swings in orders and inventory levels up the supply chain. During periods of rising demand, customers restock and rebuild inventory. In times of shortage (such as during COVID), this can also lead to double ordering. But when demand slows, customers cut back sharply to clear the excess inventory, causing a sudden collapse in new orders. An example is as such:

1. End demand changes slightly, for e.g. a 3% drop in smartphone sales

2. OEMs react conservatively, cutting chip orders by 7% to adjust inventory.

3. Distributors pull back more, fearing excess stock and cut orders by 15%.

4. Foundries see a sharp drop, leading to lower utilization rate and margin pressure.

Source: Sketchplanations

A downcycle occurs when global semiconductor sales growth peaks and begins to decelerate (i.e. January 2018 and December 2021), triggering an inventory correction across the supply chain. Once sales growth peaks, it often has a tendency to swing hard towards flat or negative region.

Source: WSTS Global Semiconductor Sales from 1987 to 2025

While situation is still fluid, we are likely approaching the next downcycle in a few months based on the latest tariff development. My prediction is that global semiconductor sales growth will peak in Q3 2025 for the following reasons:

1. U.S. tariff leads to demand shock

2. Pull forward demand

3. AI: Inventory correction and softer capex growth in 2026

U.S. Tariff Leads To Demand Shock

On 2nd April 2025, President Donald Trump declared "Liberation Day" unveiling a sweeping tariff regime aimed at reshaping global trade dynamics. Invoking a national emergency, he imposed a universal 10% tariff on all imports, with significantly higher "reciprocal" tariffs targeting specific countries: 34% on China (raising the total to 54%), 32% on Taiwan, 25% on South Korea, and 20% on the European Union, among others. The announcement triggered immediate global backlash and market turmoil. China retaliated with tariffs of up to 125% on U.S. goods, while the current tariffs on China stands at 145%.

Source: CNN

On 9th April, the Trump administration signaled potential exemptions and a 90-day pause on reciprocal tariffs to facilitate trade negotiations, though the tariffs on Chinese imports remained in effect. Few days later, it was revealed that the U.S. Customs and Border Protection agency has exempted certain electronics products such as smartphone, PC, network equipment from reciprocal tariff. As it stands today, these are the current tariff rate according to Foxconn:

Source: Foxconn

However, this is not over yet as the reciprocal tariff exemption is merely shifting these electronics product to be evaluated under a separate semiconductor tariff. On 14th April, it was revealed that the Department of Commerce has launched a probe on semiconductor tariff under Section 232 of the Trade Expansion Act of 1962. Therefore, it is highly likely that semiconductor and electronics products will be subjected to a future tariff irrespective of the deals that countries may have struck with President Trump. We know that as steel, aluminum and automotive have been subjected to Section 232 duties even if they are from Mexico or Canada.

Source: White House

Source: Federal Register

​Tariffs directly influence demand by altering prices, compelling companies to either pass increased costs to consumers or absorb them. As prices rise, demand typically declines, adhering to the law of demand. The extent of this impact on semiconductor varies across different verticals.

Source: Economics Help

Personal Computers (PC): The U.S. accounts for approximately 25% of global PC unit sales and 30% of PC value sales. Margin for PC OEMs is low, which will force them to pass on higher cost to the end consumers. In addition, 80% of global notebook assembly capacity is located in China, where China will slap a 125% tariff on Made-in-USA Intel chip and U.S. will slap another layer of tariff on China imported PC. This makes PC the most vulnerable vertical to tariff. Most of the OEMs do not plan to set up assembly plant for PC in the U.S. and have decided to further expand their capacity in ASEAN.

Smartphones: The U.S. represents about 10% of global smartphone unit sales and 20% of value sales. However, U.S. is 40% of Apple’s sales as it holds more than 50% market share in the country. This makes Apple more vulnerable than Android smartphone, which is not a good news as iPhones tend to have much higher semiconductor content than the average Android smartphone.

Servers: Server demand has less direct impact from the tariff as the ODMs have plenty of capacity in Mexico and U.S. TSMC’s Arizona Fab 21 has started mass production of 4nm, which is precisely the node that Blackwell is made.

Memory: Most of the memory manufacturing sites are located outside of U.S. in countries such as Korea, Japan, Taiwan and Singapore. Many of the memory modules and SSDs are also assembled outside of U.S. Even for Micron, they relied heavily on their NAND factory in Singapore and DRAM factories in Taichung & Japan. Their new Idaho fab will only contribute meaningful supply in 2027. Price elasticity for memory (especially NAND) is high which should lead to lower demand.

Pull Forward Demand

Pull forward demand is bad for semiconductor as it creates a high base and leads to lower demand in the future. An example is the elevated PC annual sales of >300 million units during the Covid period of 2020 to 2022, above the historical average of 260 to 270 million units. In 2023, PC shipment fell by 15% YoY to 242 million units, which is the lowest unit shipment since 2006. From the peak in 2021, unit shipment fell by 30% in 2 years.

Two sources of pull forward demand have emerged, which will put pressure on sales in 2026.

1. China consumer electronics subsidies

On January 20, 2025, China officially launched a national subsidy program for smartphones, tablets and smartwatches. The government offers a 15% discount on smartphones priced below RMB 6,000, capped at RMB 500 per device. This initiative aimed to stimulate consumer electronics demand and was part of a broader effort to boost domestic consumption. Notably, some provinces, such as Jiangsu, had already implemented similar subsidy programs as early as November 2024. The subsidies led to a significant uptick in smartphone sales. In January 2025, China smartphone sales grew by 17% YoY and 41% MoM to 29 million units. Combining with February, China smartphone sales grew by 13% YoY. Total Electronics & Appliances sales in China grew 35.1% YoY in March.

Source: Counterpoint Research

2. Tariff induces pull forward demand during the 90-day pause

Following President Trump's announcement of sweeping tariffs on imports, a 90-day pause was granted for most countries, excluding China, to allow for negotiations and adjustments. This temporary reprieve prompted both businesses and consumers to accelerate purchases of goods, particularly high-value electronics, to avoid potential price increases once the tariffs were reinstated.

Above seasonal sales strength has been seen across multiple verticals. U.S. new vehicle sales grew 4.8% YoY in Q1. According to IDC, global PC sales grew by 5% YoY in Q1 of which Macbook sales grew by 14% yoy. These are Q1 sales where the world is not aware of the big tariff spike. Post Liberation Day, panic buying should have accelerated especially with the 90-day pause.

Source: Apple

For corporates, the 90-day pause is the best opportunity for them to stock up on electronics before reciprocal tariff resumes or Section 232 tariff is implemented for semiconductor. Reuters reported that Apple had airlifted 600 tons of iPhones from India to beat the tariffs. Morgan Stanley raised their Q2 iPhone build by 10% to 45 million units, which is 5 to 15% higher than typical seasonality (destocking to prepare for the new iPhone model in September).

Notebook shipment by the ODMs in Q1 grew 3% YoY, which is 10% higher than seasonality. In particular, notebook shipment in March grew by 39% MoM. In fact, ODMs have already started to prebuild inventory since November after President Trump won the election. Both AMD and Intel have seen double digit growth for PC CPU shipment in Q4, which is much higher than flattish PC unit shipment.

​Despite elevated channel inventories, retailers and distributors are seizing the opportunity to stock up on tariff-exempt smartphones and PCs during the current reprieve. This is a temporary window of opportunity to secure inventory at lower costs. However, even if tariffs are eventually lifted, the accumulation of high channel inventory typically leads to a subsequent destocking phase.

AI: Inventory Correction, Softer Capex outlook and Geopolitical risk

1. Inventory Correction

By now, most should be familiar with the issues plaguing GB200 rack deliveries. GB200 server rack production is currently facing significant challenges due to assembly yield issues, particularly at the ODM level (Foxconn, Quanta, Wiwynn). The complexity of the GB200 NVL72 systems, which integrate 72 GPUs and 36 Grace CPUs per rack, has led to difficulties in the assembly process. These challenges have resulted in lower than expected rack shipment volumes, with estimates for 2025 reduced from an initial 50,000 racks to approximately 15,000 racks. GB300 is also facing assembly yield issues as delivery timeline has been pushed to Q1 2026.

Despite ongoing assembly challenges with NVIDIA's GB200 racks, NVIDIA's revenue outlook for the first half of 2025 remains robust. This resilience is largely due to NVIDIA's revenue recognition policy, which records sales upon the shipment of GB200 boards to ODMs, rather than upon the final delivery of assembled racks to end customers. Consequently, delays in rack assembly have led to an accumulation of inventory at the ODMs, without immediately impacting NVIDIA's reported revenues.​ TSMC has been shipping out Blackwell since November while the ODMs revenue growth has lagged. The true extent of inventory build will only be known when the ODMs report their financials over the next few quarters.

However, this inventory buildup is unsustainable for the ODMs. Operating on thin margins and facing significant working capital requirements (given the high value of GB200 components), ODMs are under financial strain. To manage these pressures, many have resorted to funding strategies such as issuing convertible bonds and GDRs to bolster their capital in 2024. Wistron is in the plan to issue 250 million new shares in GDR. While these measures provide temporary relief, the continued accumulation of unsold GB200 inventory could lead to ODMs deciding not to increase their GB200 inventory. This is perhaps why CoWoS demand forecast has been revised down. If rack delivery issues remain unresolved, there will eventually be wafer order cut from Nvidia.

2. Weaker sales outlook for FAMG and elevated capex intensity

The ongoing trade war does not bode well for companies such as Meta, Amazon and Alphabet. Meta and Alphabet are heavily reliant on advertisement sales which is highly correlated to the state of the economy. Both Temu and Shein have significantly reduced their advertising spend on Google and Meta platforms. Meta’s share price has since declined more than 33% from its February peak. Meanwhile, over 50% of Amazon’s third-party sellers are based in China, highlighting the platform’s exposure to the ongoing trade war between China and U.S.

Source: Adweek

Source: SMEC

Capex intensity (capex-to-sales ratio) is now at an all-time high, putting pressure on free cash flow. FAMG are expected to spend 50-70% of their operating cash flow on capex in 2025. Capex can rise either through revenue growth or higher capital intensity. In 2024 and 2025, the sharp spike in capex spending by the FAMG has led to a notable decline in free cash flow. Historically, during periods of economic uncertainty or slower growth, the FAMG have responded with inventory digestion or capex moderation, as seen in 2019 and again in early 2022.

Before ChatGPT’s breakout in late 2022, there was an earlier wave of AI enthusiasm sparked by AlphaGo’s 2016 victory over Lee Sedol. During that period, shares of SK Hynix and Micron surged over 300% from 2016 to their 2018 peak, while Samsung had already begun mass production of HBM.

Source: Micron in 2018

In 2019, a slowdown in revenue growth prompted capex reductions across the FAMG group. This also coincides with the trade war that President Trump started in his 1st presidency. Meta cut its capex guidance twice, lowering it from an initial $18–20 billion to $16–18 billion, as sales growth decelerated due to user saturation in the U.S. and the impact of GDPR in Europe. Alphabet also saw a significant moderation in capex following its slowest quarterly sales growth since 2015. For Microsoft, capex growth moderation reflected a digestion phase after heavy infrastructure investments in the past 2 years.

In 2022, FAMG cut capex in response to a sharp slowdown in revenue growth and rising macroeconomic uncertainty. Soaring inflation, interest rate hikes, and weakening consumer demand prompted a shift from aggressive expansion to cost discipline. Meta and Alphabet scaled back infrastructure and hiring plans, while Microsoft and Amazon focused on optimizing existing capacity after years of elevated investment during the pandemic driven digital surge.

While the FAMG have committed to their capex plans for 2025, the announcement of Liberation Day has reintroduced uncertainty into the economic outlook. Any meaningful hit to revenue growth could lead to a moderation in capex expansion in 2026. Long-term investment in AI remains intact, driven by the continued validity of the 3 Scaling Laws. However, digestion periods like those seen in 2019 and 2022 can still occur, even in the presence of transformative technologies like convolutional neural networks (CNNs) and Scaling Law (Kaplan, 2020).

3. Geopolitical risks and regulations

There are also additional geopolitical risks such as the recent ban of NVIDIA’s H20 shipment to China. NVIDIA has to take a $5.5 billion charges with revenue impact of at least $10 billion. ​In January 2025, the Biden administration introduced the AI Diffusion Rule, a comprehensive export control framework aimed at regulating the global distribution of advanced U.S. AI technologies. AI Diffusion Rule is set to be take effect from 15th May 2025 if it is not reversed by the Trump administration. This will have a big impact on GPU demand coming from Sovereign AI across Asia and Middle East.

Silver Lining In The Dark Cloud

While the dark cloud has gathered, several factors suggest that we do not have to be overly pessimistic of semiconductor companies. This is because market always looks forward for semiconductor stocks. To put it in another way, semiconductor stocks often bottom ahead of the bottom in semiconductor sales growth.

1. The market has partially priced in a certain degree of downcycle

In past upcycles, share price corrections typically occurred only after global semiconductor sales growth peaked and began to decline. This time, however, SOXX peaked early in July 2024, even as the 3-month moving average of global semiconductor sales growth has remained elevated.

The current 37% drawdown in SOXX is already approaching the 49% seen during the 2022 downcycle. While historical drawdowns aren't always directly comparable, it's worth noting that the sector saw much deeper declines of 60-70% following the Dot-Com Bubble and the 2008 Global Financial Crisis. Conversely, corrections were more modest at more than 30% during the 2018 and COVID downturns, when macroeconomic conditions were relatively more benign.

2. Asynchronous cycles across semiconductor verticals

What makes this cycle unique is the lack of synchronization across semiconductor verticals. Smartphones, PCs, and memory were the first to correct in 2022 and also the first to rebound in 2023. The strength of the current upcycle has been driven almost entirely by AI related demand, while most other end markets remain sluggish. Notably, automotive semiconductor companies are still working through inventory corrections nearly three years after SOXX peaked in December 2021! It is more appropriate to say there are multiple cycles within the different verticals.

This means that certain segments may bottom earlier than others. Using peak-to-trough drawdowns as a guide, semiconductor equipment companies have seen declines of 40–50%, driven largely by concerns over their China revenue exposure. Lower valuations are a positive for semicap, as the Big Four allocate a significant portion of their free cash flow to do share buybacks. Meanwhile, share prices of analog semiconductor companies are approaching their 2023 lows, reflecting their high sensitivity to weakness in global industrial and automotive demand although they are already under-shipping actual demand.

On the other hand, AI related stocks have slightly outperformed the broader SOXX drawdown, with shares of Broadcom, NVIDIA, and TSMC declining around 33%. Historically, however, it’s often the hottest theme of the upcycle that faces the sharpest correction in a downcycle. Again, think about the carnage for automotive semiconductor companies after the 2021 shortage cycle.

In both the 2018 and 2022 downcycles, NVIDIA’s share price fell over 60% from its peak. Jensen has historically opted for steep inventory charges over price cuts, an action that has often marked the bottom in NVIDIA’s share price in 2019 and 2022. While the $5.5 billion charge helps to clear the Hopper inventory risk, we need inventory charge on Blackwell.

Meanwhile, TSMC’s ADR is still trading at a 15% premium to its Taiwan listed shares (2330.TW). The gap narrowed to nearly 0% at the stock’s bottom in Q3 2022. TSMC has just reaffirmed its full-year guidance for 2025, but is it a bottom when the world’s most important foundry hasn’t even cut guidance yet? We have also not seen any downward guidance revision from Broadcom and NVIDIA.

​A slowdown in AI capex poses significant challenges for DRAM manufacturers. HBM3, for instance, consumes approximately three times the wafer capacity of DDR5 owing to its larger die size and lower yield rates . This shift has led companies like Samsung, SK Hynix, and Micron to allocate more wafer capacity toward HBM and reducing the available supply for DDR5. The recent U.S. export ban on Nvidia's H20 AI chips to China is expected to reduce their revenue by about 1%, but it could lead to a 3% increase in DRAM bit supply as wafer allocations revert from HBM back to standard DDR5 module . This reallocation may exacerbate oversupply issues in the DRAM market, potentially impacting pricing and profitability for manufacturers.

3. Investment thesis for AI is intact as Scaling Laws remain

Today, we have three Scaling Laws in AI: Pre-Training Scaling, Post-Training Scaling, and Test-Time Compute Scaling. While Pre-Training Scaling may be nearing its limits in a few years, the latter two remain highly promising. As models grow, emergent properties continue to surface which reinforces the case that more compute remains a viable path to breakthroughs in AI capabilities.

Source: Jensen Huang at CES 2025

This dynamic also feeds into Jevons Paradox: as AI becomes more powerful and cost-efficient, its utility rises, spurring even greater usage rather than reducing demand. The emergence of AI agents further amplifies this trend, as their ability to automate tasks, generate outputs, and interact with other systems autonomously creates exponential demand for inference compute. AI agents are expected to improve significantly and achieve adoption readiness by the end of the year. The long-term investment thesis for AI remains intact, as it has since 2016. However, this doesn't preclude painful digestion periods like those seen in 2018 and 2022 from occurring along the way.

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Conclusion

The semiconductor industry is no stranger to cycles and that’s exactly what has captivated me so deeply. Its inherent cyclicality is driven by capacity mismatches, inventory imbalances and unpredictable demand shocks. While the current cycle is shaped by unprecedented geopolitical developments, AI driven optimism, and asynchronous recoveries, it echoes the same dynamics that have defined the past 70 years.

As we head into what appears to be another downcycle, investors must brace for further turbulence while keeping their eyes on the long arc of technological progress driven by Moore’s Law. The road to $1 trillion in semiconductor industry revenue by 2030 will not be linear, but it is a path worth navigating. Lower valuations and falling share prices are often healthy first steps toward an eventual bottom.

For investors, the best way to prepare for the coming semiconductor downcycle is to stay focused on high-quality companies positioned to benefit from strong structural tailwinds once the industry recovers. If you find the content is useful, do subscribe to discover global semiconductor leaders worth owning for the next cycle.

Source: Tokyo Electron, Lam Research, KLA, Kokusai

The WFE companies are not expecting a big increase in overall WFE spend in 2025. While Lam Research and KLA are looking at mid single digit growth in WFE, Tokyo Electron and Kokusai are looking at a flattish year. This is still slightly better than the expectation of a decline in WFE in 2025 due to weak memory outlook and capex cut at Samsung, Intel.

NAND > TSMC > DRAM > Logic

Source: Tokyo Electron, Lam Research, KLA, Kokusai

Contrary to what some might expect, NAND is actually the strongest growth driver for WFE in 2025. Tokyo Electron expects NAND capex to double while Kokusai is seeing a 25% increase. Both Lam Research and KLA are also seeing growth in NAND capex. On the other hand, outlook for both logic and DRAM are flattish.

In NAND, the industry is looking to transition the current installed capacity to higher layer counts to achieve better device performance at lower bit cost.

But at the same time, on the last call, I mentioned this point that about 2/3 of the bids are still being manufactured on nodes below 200 layers. And what happens as you move above 200 layers is not only do you have to upgrade the existing tools, but you have to start adding additional tools to deal with the complexity of that transition.

Source: Lam Research

NAND prices continue to decline and major producers are cutting production level, so no one is really expanding greenfield capacity. As NAND spending has been at a very subdued level for 2 years (down 50% from 2022 peak), memory makers are starting to upgrade their layer count again. We are definitely not in the new era of NAND that Western Digital was talking about where there is an end to the layer race.

Source: Western Digital - The New Era of NAND

Among the major NAND producers, it is likely to be Samsung, Hynix and YMTC that are driving the upgrade cycle. Samsung is upgrading its V6 NAND to V8 this year and will be developing 400L NAND in 2026. Hynix will be upgrading to 321L NAND this year, followed by 400L NAND in 2026. YMTC is working hard to achieve a breakthrough to 160L NAND with the help of AMEC in China. Lam Research is no longer able to supply etching tool to YMTC. While Kioxia will like to spend more, they are constrained financially and by their partner Western Digital.

Logic - TSMC is the kingmaker

Leading edge logic demand is strong as TSMC is looking at mid-20% growth in revenue for 2025. TSMC had guided for mid 30% in capital intensity last year so it was no surprise that it raised its capex from $ 29.8 billion in 2024 to $38 - 42 billion in 2025. With a 20% revenue CAGR from 2024 to 2029, TSMC will continue to spend more in capex on the leading edge. N2 is set to start mass production this year and ramp in volume in 2026. As the number of new tape-out for N2 in the first 2 years will be higher than both N3 and N5, N2 is a big volume ramp in 2026 and 2027. N2 is TSMC’s 1st GAA node, so this will disproportionately benefit ASMI and Lam Research which are the main ALD provider.

Most will have known that Samsung and Intel have cut their logic capex. Intel has further cut their gross capex in 2025 from $20-23 billion to $20 billion. This is a 20% capex cut in 2025 after a 20% capex cut in 2024. Intel Foundry is not getting any significant customer in the next 2 years. Nova Lake, which is the next generation client CPU after Panther Lake, will continue to have some tiles outsourced to TSMC. Granite Rapid has been delayed to 1H 2026, while Falcon Shore will no longer be sold externally.

For Samsung, next generation Galaxy S25 will be 100% Qualcomm chipset as they are not using their in-house Exynos. This is the 2nd time in recent year since S23 that Exynos is not used in Samsung’s flagship phones. As Samsung’s lead edge node is progressing far worse than Intel, it has been losing clients such as Qualcomm to TSMC. TSMC has effectively monopolised N3 and beyond node. I highly doubt Samsung can turnaround the foundry business unless it gave up on the leading edge. The big question for Samsung Foundry is what are they going to do with the Taylor fab. Equipment move-in for Taylor fab has been paused and the ramp has been delayed from 2024 to 2026. Because N4 yield is unsatisfactory, Samsung is betting instead on N2 ramp in 2026 to save them. Samsung had earlier announced that Taylor fab investment is $17 billion and total spending in Texas will run up to $40 billion. Chips Act grant was subsequently cut to $4.75 billion from $6.4 billion. Samsung is not going to get any large order for N2, so this could become a $17-40 billion asset that has to be written off eventually.

DRAM

DRAM price continues to decline with the ramp of CXMT output, while HBM demand remains very strong. With DDR4 oversupply, DRAM producers are shifting their product mix to DDR5 and HBM. Although DRAM price is expected to recover in 2H 2025, overall DRAM capex will be muted. Both Hynix and Micron are constrained in their ability to expand capacity meaningfully due to a lack of cleanroom space. Hynix has guided for limited incremental capex with the mix shifting more towards infrastructure for Yong-in fab in 2027. Hynix’s M15X equipment spend will be about $10 billion spread over 2025 and 2026. Micron is waiting for Idaho and New York fab to be ready in 20-27 and 2028. Samsung is guiding for flattish capex in 2025 with a reduction in foundry and increase in memory (more for NAND).

China

China was a hot topic for WFE manufacturers as it accounts for 40% of their revenue in 2024. With the export control and pull-forward demand (especially DUV) from China, it was inevitable that China revenue will decline. China is now going to be 30% of revenue for the WFE producers and likely be even lower in 2026. ASML’s China sales is a leading indicator for the other WFE’s China sales. Both KLA and Lam have seen a $500 million and $700 million impact from export control respectively.

Another angle that investors often miss is how fast the China WFE manufacturers are ramping up in capabilities. Because of export control, YMTC has to rely on local manufacturer such as AMEC for etching tool. The top 3 WFE manufacturers in China (Naura, AMEC and ACM Research) have grown their revenue by more than 30% to USD 6 billion. Naura expects local WFE companies to grow their revenue from USD 8.2 billion in 2024 to USD 11 billion in 2025 (11% global market share). The 33% growth is very impressive, considering China WFE will be down 15-20% in 2025. Domestic import substitution rate for WFE will be 35% in 2025.

China WFE demand is expected to decline as CXMT is slowing down their capex in 2025 while mature logic is suffering from overcapacity. On the other hand, YMTC is expected to ramp up its 160L investment after being crippled temporarily by the export control.

Share Shift

Tokyo Electron has secured mass production POR for NAND channel hole etching with its cryogenic etching for 2026. Given Tokyo Electron’s market share of 10-15% in 3D NAND etching, this will be a market share gain opportunity from Lam Research. However, I do not expect Tokyo Electron to monopolise cryogenic etching as Lam Research has come out with similar product.

Lam Research has secured POR for dry resist for DRAM, which will take away some market share from Tokyo Electron.

ASML - Peak lithography until High-NA arrives in 2030

The bigger share shift opportunity remains the shift towards materials engineering from lithography scaling for the rest of the decade. Deposition and etching will outperform as lithography intensity is reduced. Logic metal pitch will only shrink by 10% from 23nm in 2023 to 21nm in 2027 compared to the 20% shrink from 28nm in 2020 to 23nm in 2023. TSMC’s N2 node is reliant on the Gate-All-Around (GAA) architecture which will favor Atomic Layer Deposition (ALD) equipment and etching tool. ASMI is the biggest beneficiary of single-wafer ALD which will continue to grow in important into CFET and 3D DRAM. Lam Research is seeing its ALD revenue growing by at least 50% in 2025 from $1 billion in 2024. Lam Research will only benefit from the use of lateral etching in GAA.

Source: ASML Investor Day

Source: Lam Research

As TSMC moves towards A16 in 2026, backside power delivery will be the key driver. EV Group will be a big beneficiary as the main provider of wafer-to-wafer hybrid bonder. CMP tool (Applied Material and Ebara) and grinding tool (Disco) will also benefit from content growth.

ASML will outperform WFE again when High-NA EUV is adopted by TSMC near the end of the decade. 5 years is a long time and it remains to be seen if there will be further delay in adoption. 3D DRAM is also a threat to ASML in the longer term, although ASML don’t see it happening in 2030.

Conclusion

With China de-risked and the underperformance against SOXX, it might be time to relook at the WFE manufacturers again. Companies such as ASMI, Lam Research and KLA are clear WFE share gainers over the next few years. Tokyo Electron and Applied Material will benefit to a smaller extent, while ASML’s sales underperformance will be seen from 2026. China sales will continue to dwindle for foreign players as domestic substitution continues.

2026 should be a stronger year in capex spending as TSMC continues to increase capex to meet the demand of N2. Hynix and Micron will also start to pull in equipment in 2H 2026 for their new greenfield plants.

1. Revenue guidance for 2025 is now EUR 30-35 billion as compared to 30-40 billion earlier

2. Low NA EUV shipment will now be <50 units in 2025 as compared to expectation of 65-70

3. Gross margin of 51-53% in 2025 as compared to 54-56% earlier

4. Net booking of only EUR 2.6 billion (EUV was EUR 1.4bn or 7 units) as compared to expectation of more than EUR 5 billion

A shipment reduction of more than 20 EUV units is shocking for an equipment with lead time of more than a year. In addition, memory customers are increasing their adoption of EUV layers.

It is not China

The sharp decline of China business was what first came to mind. ASML expected China to go back to a more normalised percentage of sales (20%) as it had been in the backlog. China had been more than 40% of sales in the last few quarters, so this implies a decline of 30% yoy in 2025.

China had been one of the key risks for semicap companies given the high contribution to many semicap companies in the downcycle. We can’t expect China to continuously expand capacities at all costs. There are signs that SMIC, Hua Hong and YMTC are no longer expanding capacities as aggressively as they were before. In addition, there had been quite a bit of demand pull-in for fear of further export restriction by the US government.

However, guidance on DUV was not affected much due to the sharp rise in DUV orders from non-China customers.

Samsung and Intel are the culprits

From the press release, it certainly seems that both Samsung and Intel are having much slower capacity ramp as a result of their inferior technology and hence lack of customer.

"While there continue to be strong developments and upside potential in AI, other market segments are taking longer to recover. It now appears the recovery is more gradual than previously expected. This is expected to continue in 2025, which is leading to customer cautiousness.

Regarding Logic, the competitive foundry dynamics have resulted in a slower ramp of new nodes at certain customers, leading to several fab push outs and resulting changes in litho demand timing, in particular EUV. In Memory, we see limited capacity additions, with the focus still on technology transitions supporting the HBM and DDR5 AI-related demand.

This is nothing too surprising for those who have followed the 2 IDMs. 2 months ago, Intel announced that they will reduce gross capex by more than 20% to $25-27 billion in 2024 and $20-23 billion in 2025. Intel had delayed the construction of 2 fabs in Ohio and 2 fabs in Germany by more than 2 years.

Samsung had delayed its Taylor fab from 2024 to 2026 due to poor yield. Samsung’s execution on advanced nodes has lagged even that of Intel. For Samsung’s Galaxy 25, Snapdragon 8 Gen 4 will be adopted instead of the internal Exynos chip. Snapdragon 8 Gen 4 is fabbed at TSMC N3 instead of Samsung. Without a significant internal or external customer, it is no surprise that Samsung has cut its foundry capex massively.

Didier Scemama Excellent. And a follow-up to that would be, how much of the pushout is a reflection of just the end demand being pulled versus maybe several of your customers struggling with process technology and attracting effectively customers to justify the construction of those factories?

Christophe Fouquet Chief Executive Officer I think it's both. So it's a mix of that. I think that we learned the slower recovery first, because I think this affects every single customer. So we are still quite optimistic about AI. I think today without AI, the market would be very sad, if you ask me. But for the rest, I think our customer continues to confirm, that when it comes to [indiscernible], when it comes to PC or when it comes to automotive, the recovery is not what I think anyone had wished for. And that affect, I would say, a large part of our customer on all segments and application.

I think we also indeed mentioned as well some competitive dynamic on logic. I think that also has been express advance in the press in the last 3 months. I think that's not really new for you. And this also contributed to some of the pushout. So I think those 2 things are really the 2 dynamics that have come up in the last few months to a level where our customers basically started to really make, I would say, a decision that were in line with their expectations, both on the total market, but also maybe, in some cases, on the share they may end up having in some of the Logic market.

Source: Q3 2024 Earnings Call

This is further confirmed during the earnings call when Didier Scemama from BofA asked if the pushout is due to demand or customers struggle with technology. ASML CEO said that customers are making decision in line with their expectation “on the share they may end up having in some of the Logic market.”

In its preliminary Q3 preview, Samsung attached an apology letter. We might be seeing Samsung finally comes to term with the horrible state of its foundry process. Samsung could also be cutting some of the EUV orders for DRAM as its 1b nm process is unable to deliver the requirement needed for HBM3e qualification by Nvidia.

TSMC is increasingly becoming a monopoly at the advanced node for Logic

Capex today is capacity and market share in the future. If TSMC does not spent on 2nm capex in 2023, there will not be any 2nm revenue in 2025.

As I have written earlier in an article on Morris Chang’s 3 KPIs, capex today represents maximum potential market share in the future. Even if Intel’s 18A came to fruition, it will have limited market share without the necessary capacity. Customers have to believe that foundry have sufficient capacity for them before they choose to tape-out with the foundry.

Not only is Samsung losing its internal Exynos customer, but it is also increasingly likely that there will be partial outsourcing of Panther Lake tiles to TSMC in 2026 beyond Arrow and Lunar Lake. Panther Lake was supposed to showcase the success of 18A, but capex cut has happened, and Intel has become more active in its engagement with TSMC of late.

This is not TSMC gaining market share in foundry, but foundry gaining shares from the IDM. And at the advanced node, it looks like there is only 1 credible company remaining to drive the roadmap. This is not healthy for the industry in the long-term, but it was always meant to be with the economics of Moore’s Law

What does it mean for ASML if TSMC is increasingly becoming a bigger part of its EUV revenue? We have seen TSMC putting pricing pressure on ASML in its negotiation as TSMC recognised its dominant position in the industry. Lead time at ASML is also no longer as high as it used to be after capacity expansion.

When it comes to flexibility, I think there is some flexibility to the extent that orders would come in, in Q1. I think we'd still probably be able to cater to those orders in 2025. I think we build in sufficient flexibility to create that.

Source: Q3 2024 Earnings Call

In the near term, ASML will still have SK Hynix and Micron as they are ramping up their 1b nm and 1-gamma respectively. However, memory is cyclical in nature, and we are definitely nearer to the end of the semiconductor upcycle than the start of it.

EUV intensity is set to reduce in the next few years

ASML enjoyed higher share of WFE as EUV penetration rose rapidly from N7 to N3. However, the number of EUV layers is set to plateau as architecture changes such as GAA and Backside Power Delivery took place. The additional process steps will benefit mostly deposition and etching companies, especially for ASM International with its ALD and Epitaxy tool. TSMC has eliminated a couple of EUV layers from N3B to N3E. Number of EUV layer will be relatively flat at low 20s for N2 and A16 as TSMC relied on GAA and Super Power Rail respectively.

Eventually, the industry will still have to adopt High NA EUV as it further shrinks the transistor. This will happen nearer to the end of the decade, which is when ASML will start to gain share of WFE again as it did from 2018.

TSMC’s CoWoS capacity is in the focus after the acquisition of Innolux Tainan 4^th plant for NT$ 17 billion. The Innolux plant has been designated as AP8 which will become the 7^th advanced packaging plant of TSMC. Given the existing infrastructure, AP8 can start production in 2^nd half 2025 after some modification and equipment move-in. AP8 is significant as the total area is more than 96,000 sqm which is 9x larger than TSMC’s Zhunan AP6 plant.

Source: TSMC’s CoWoS-L

Currently, TSMC has a total of 5 advanced packaging plants located in Taiwan. AP1 in Hsinchu will become a R&D fab. AP2 in Tainan is for micro bumps and small amount of CoWoS capacity. AP3 in Longtan is mostly catered to InFO (Integrated Fan-Out), which Apple is still the main user today. AP5 in Taichung and AP6 in Zhunan are the main plants for CoWoS.

Source: TSMC

TSMC's plans to ramp up the AP7 facility in Chiayi have faced delays due to archaeological findings at the original site. As a result, the ramp-up will now take place at a 2^nd site in Chiayi Science Park. Looking ahead, TSMC has ambitious plans to establish multiple advanced packaging plants in the Chiayi area.

As TSMC’s CEO C.C. Wei guided in the latest earnings call, “Talking about CAGR of those kind of increase of the CoWoS capacity, now, it's out of my mind. We continue to increase whatever, wherever, whenever I can, okay. The supply continues to be very tight, all the way to probably 2025, and I hope it can be eased in 2026”.

TSMC’s CoWoS capacity will grow from 13k wpm at the end of 2023 to 30-35k at the end of 2024 and 70-80k at the end of 2025. CoWoS capacity in 2025 is now significantly higher than the street’s estimate just a few months ago. TSMC continues to acquire more lands in Taiwan, so it is still too early to judge the final CoWoS capacity at the end of 2026. It will at least be 100k wpm by the end of 2026.

Why is so much capacity needed?

The rapid expansion of CoWoS capacity indicates that AI chipsets demand forecast of Nvidia, AMD and the system companies (Google, Amazon, Meta and Microsoft) remain very postive. CoWoS is mostly used for HPC and AI applications where HBM is integrated with the logic chip in a package. TSMC has managed to capture almost 100% market share of the AI chip market, and this has become a significant bottleneck.

Bigger package size is an ongoing trend and TSMC is making the preparation for the bigger package. Reticle size is the biggest possible die size at 858mm² (26 x 33mm) based on the field size and photomask. Given that many chips are at close to reticle size, making bigger package through advanced packaging is the way to go to drive higher compute performance. Blackwell at 3.3x reticle size is significantly bigger than Hopper and the next-generation Rubin will come in at 4.0x reticle size to fit 12 stacks of HBMs. The larger package size consumes more CoWoS capacity especially as you are fitting rectangles in a circle.

Source: TSMC

Source: ASE, BofA

One solution is panel level package (PLP) which will lead to smaller area loss. However, PLP is unlikely to become a mainstream solution until at least 2027 as the equipment ecosystem is not ready. Warpage and breakage are key problems that TSMC must resolve in addition to qualifying backend equipment for the bigger panel size. Equipment must be ready to handle much bigger panel of up to 60x60cm. TSMC is expected to settle on the size of the panel soon, so that the ecosystem can start preparation for it.

Equipment suppliers are obvious beneficiaries while it lasts

Given the aggressive capacity expansion, equipment vendors will do very well in 2025 with the ramp of AP7 and AP8. Key suppliers of advanced packaging equipment are ASMPT, BESI, Camtek, Onto Innovation and SUSS MicroTec. ASMPT is the market leader for TCB (Thermo Compression Bonder) tool and is awaiting final qualification for TSMC’s Chip to Wafer application. BESI is the market leader for hybrid bonder, but we are unlikely to see a big ramp in TSMC’s SoIC capacity (4k wpm in 2024 to 8k wpm in 2025) next year. Onto has a much higher share of TSMC’s advanced packaging capacity than Camtek. SUSS MicroTec is a provider of temporary bonder debonder tool and UV scanner.

In recent months, local Taiwanese supply chain companies like All Ring Tech, Grand Process Technology Corp, Scientech, and Chroma ATE have emerged as standout performers in share price. They have achieved significant market share gains due to strong collaboration with TSMC, allowing them to align their offerings with the needs of the semiconductor giant. All Ring Tech provides underfill dispenser, AOI and heat sink machines. Both Grand Process Technology and Scientech are providers of cleaning equipment for the CoWoS process. Chroma ATE has been qualified by TSMC to be the main equipment vendor for the metrology tool for CoWoS’s redistribution layer measurement. Some of these are customised tools for TSMC, which is another barrier of entry for other foundries or OSATs.

Source: Yahoo Finance

Expectations are high and share price of related companies has gone through the roof. How long the party lasts hinge on whether TSMC will continue to expand CoWoS’s capacity aggressively in 2026 and 2027. Given that backend capex is only 10% of TSMC’s total capex, the financial risk is low for TSMC even if forecasts from customers turn out to be over optimistic. This will certainly be an important area to follow as major innovations such as hybrid bonding, co-packaged optics and panel level package are set to take off in the medium term.

In an interview 8 years ago, Morris Chang (founder of TSMC) brought up the 3 most important performance indicators that he used to monitor the health of TSMC.

1. ASP growth

2. Capex

3. R&D expenditures

ASP growth represents pricing power which is an indication of the current technological superiority of TSMC’s process.

Capex today is capacity and market share in the future. If TSMC does not spent on 2nm capex in 2023, there will not be any 2nm revenue in 2025.

R&D expenditure correlates to the future technological superiority of TSMC’s process.

As long as all 3 KPIs are going up, Morris Chang knew that TSMC is on the right track. And that is what Morris Chang did when he returned in 2009 to replace Rick Tsai (current CEO of Mediatek) as the CEO of TSMC. He immediately doubled TSMC’s capex in 2010 to USD 5.9 billion, which allowed them to capture the smartphone market. R&D expenditure which had been flat for a few years was accelerated. ASP began to inflect in 2012 after years of decline.

All 3 indicators continue to show positive long-term trend ever since Morris Change came back in 2009. In particular, TSMC’s ASP started to grow at high single digit per year from 2019 to 2021 and further rose to double digit growth rate in 2022 and 2023. 2018 was the introduction of TSMC’s N7, the 1st node where TSMC achieved process node parity with Intel. The rest was history.

Source: TSMC

Intel’s Opex Cut

Reductions across OpEx, CapEx and cost of sales totaled well over $10 billion in direct savings in 2025 and provides clear line of sight to a sustainable model with the ongoing financial resources and liquidity needed to support our long-term strategy.

We remain confident that we have and will continue to make the investments needed to drive long-term shareholder value and we view cost discipline as the compass that drives effective execution, helping teams stay on track to both prioritize and achieve measurable results. The operational and capital improvements we are driving will be especially important as we manage the business through the near term.

Source: Intel Q2 2024 earnings

Contrary to Morris Chang’s turnaround strategy in 2009, CEO Pat Gelsinger decided to cut operating expenses (R&D is 2/3 of total opex) from $21.7 billion in 2023 to $20 billion in 2024, $17.5 billion in 2025 and reduce again in 2026. All these while the cost to keep up with Moore’s Law continues to go up as we navigate through GAA, Backside Power Delivery, High-NA EUV and CFET.

Gross capex will also be cut by 20% to $25-27 billion in 2024 and $20-23 billion in 2025. On the other hand, TSMC’s capex will continue to go up in 2025 as capital intensity is maintained in the 30s while revenue is expected to grow.

Source: Intel

Source: Bernstein

I have decided to use gross margin as a proxy of ASP for Intel. If the foundry process is not competitive, Intel will have to outsource more to TSMC. This is what is happening with the outsourcing of Lunar Lake to TSMC. Although Intel is bringing in Panther Lake in-house, next-generation Nova Lake is likely back to TSMC again.

I think on the margin front, I talked about our kind of tempered view of gross margins next year, given the ramp of Lunar Lake, which with memory and package and almost all of the material getting sourced outside and they're seeing -- we're seeing inflation in that space. That is impacting it. But that part is followed by Panther Lake. That comes back into the fab.

When Pat Gelsinger came back to Intel in 2021, he did raise capex and R&D spend in 2022. However, 2022 was also the year where Intel started to suffer from negative free cash flow. Inventory correction happened for PC as demand was brought forward during Covid.

Here are 3 more charts to illustrate why Intel was never able to keep up with the 3 KPIs earlier.

Source: Intel

Having missed the smartphone and AI product cycle, Intel is left with a stagnant CPU market. Superiority in process node manufacturing was a key moat for Intel’s product, which got worse when TSMC achieved process parity with Intel after 2018. Competition in the form of AMD, AWS’s Graviton, Apple’s M series, Qualcomm X Elite is increasing as these companies are able to fight on a more even playing field with the help of TSMC. Today, Microsoft, Meta and Google are also in the process of designing their in-house ARM-based CPU to be manufactured at TSMC. The rise of Nvidia was another significant hit to Intel as demand for AI processors cannibalizes server CPU demand.

And then ultimately, I think on pricing, it will really come down to when we have a competitive process, and we have competitive products running on a competitive process, and we're delivering what the customers want. That helps us in terms of the pricing dynamic

Source: CFO of Intel in Q2 2024 earnings

At best, Intel is only able to defend against further share loss in a stagnant CPU market even if it has a competitive product on competitive process. Revenue this year will be closer to where it was in 2011 when 28nm was in production. Cost of R&D required for CPU and foundry process have gone up significantly since. Without a growing revenue base, there was no way Intel will have the cash flow to sustain investment in the foundry to achieve its 2030 goal.

Given the ambitious plan, Intel should have removed dividend the moment there was buy-in on Pat Gelsinger. Free cash flow has turned negative to the tune of $15 billion a year. Leverage is now at 40% net debt to equity and multiple rating agencies have downgraded Intel’s bond this year.

1. Intel Corp. Ratings Placed On CreditWatch Negativ | S&P Global Ratings (spglobal.com)

2. Fitch Downgrades Intel's Ratings to 'BBB+'

3. Moody's Investors Service downgrades LT- local currency credit rating of Intel to "A3"

Supported by Chips Act money, Intel will not be a going concern. However, Intel certainly does not have sufficient resources to support the growth of both foundry and products. Moore’s Law is brutal, and it is the ultimate driver of this increasing return to scale business where the winner becomes bigger over time. Intel will achieve mass production of 18A, but this does not lead to any significant foundry business revenue. TSMC’s mass production of A16 in 2H 2026 will further erode the advantage of Intel’s Backside Power Rail.

Intel is underperforming on Mooris Chang’s 3 KPIs once again and the outlook is not bright given declining revenue, negative free cash flow and rising gearing. There is just no way out for Intel unless there is significant revenue growth in either its CPU product or the foundry business. Moore’s Law requires ever increasing investment and that is only possible if you have improving revenue & cashflow.

AT TSMC’s annual symposium, A16 was revealed as the next node after N2. Backside Power Rail has now been removed from N2P. A16 will be TSMC’s 1st node to combine gate-all-around (GAA) nanosheet FET with a better version of BPR called Super Power Rail (SPR). A16 will start production in 2H 2026, half a year after N2P.

This is not simply renaming N2P as A16. A16 will see high single digit density gain, 8 to 10% speed improvement at same voltage and 15-20% power reduction at the same speed vs N2P.

Intel’s PowerVia vs TSMC’s Super Power Rail

Back at AMAT’s investor day in 2022, they highlighted the differences between the different approaches to Backside Power Distribution. Intel has chosen Power Via as the technology roadmap for 20A and 18A. TSMC has decided to choose Backside Contact to S/D (Source and Drain) for its Super Power Rail. Super Power Rail has the best scaling at the cost of much higher complexity than the Power Via adopted by Intel. AMAT had talked about the differences in its masterclass in 2022.

AMAT Masterclass 2022: “The third approach is significantly more complex. We are developing integrated material solutions as well as co-optimized solutions to enable this third approach. The approach increases logic density by around 30%, which is equivalent to two nodes of EUV scaling”

Intel uses Nano TSVs to connect the backside power network to the transistor, while TSMC’s approach is to do a direct contact of the backside power network to the source and drain of the transistors.

TSMC’s process leadership position is widening over Intel

At Intel’s Foundry Day, it was revealed that 18A will ramp in 2026 with big volume ramp in 2027. This was a slight delay from what Intel stated in 2022 Q4 earnings that 18A will achieve manufacturing readiness in 2H 2024.

TSMC 2022 Q2 earnings

“N2 deliver full node performance and power benefits to address the increasing need for energy-efficient computing, with 10 to 15% speed improvement at the same power or 20% to 30% power improvement at the same speed and logic density of more than 20% increase as compared with N3E.”

TSMC 2023 Q2 earnings

“Backside power rail will provide 10% to 12% additional speed gain and 10% to 15% logic density boost on top of the baseline technology. We are targeting backside power rail to be available in the second half of 2025 to customers with production in 2026”

TSMC CEO has previously stated that Intel’s 18A is similar to TSMC’s N3P in PPA. N3P is TSMC’s iteration of its N3E and will ramp in very high volume in 2H 2024. Given the double-digit improvement of N2 over N3E and single digit improvement of A16 over N2, TSMC is only widening its process leadership over Intel. With only half a year of gap between 18A and A16, Intel will at most be able to secure small clients for its foundry business.

A16 could even be better than Intel’s 14A in 2028 despite Intel’s use of High-NA EUV. Pat Gelsinger: “Generally, when we say a node, it's at least double-digit power-performance improvements per node. You know, I think our cut off is 14% or 15%"

AMAT and ASMI are beneficiary of A16 with the adoption of Super Power Rail and potentially higher layer count of ALD.

SK Hynix Q1 2024 results

SK Hynix reported a gross margin of 39% which was 19% higher than previous quarter (includes 7% reveral of inventory valuation loss). DRAM ASP grew by more than 20%, while NAND ASP grew by more than 30%.

While this was a strong beat, HBM3e has yet to meaningfully contribute to its revenue yet. 8-Hi HBM3e will ramp from Q2 for H200, while 12-Hi HBM3E will be ready in Q3 2024 for GB200. With each generation of HBM having higher ASP than the previous, we are definitely far from peak earnings for Hynix.

Hynix has also confirmed that hybrid bonding has been pushed back after the height relaxation by JEDEC. Productivity and quality issues are the main concerns in the early day of adoption, while more metrology and inspection will be needed. The likely timeline for HB adoption by Hynix will be in 2H 2028 when $3.8bn Indiana plant for advanced packaging is ready.

Hynix also announced a new fab M15X in Cheongju for DRAM to be opened at the end of 2025. This was not entirely a surprise as I have written in earlier article about how Hynix is constrained by Wuxi fab. HBM3E requires the use of 1b nm, while Wuxi Fab is stuck at 1a nm due to the restriction of EUV in China. M15X has the advantage of being adjacent to the current M15, which has TSV capacity for HBM.

Is the DRAM cycle over because Hynix announced a new fab? The fab will only be ready for production in 2026. Given Micron is also opening a new fab in 2026, this does add to the risk of a reversal in DRAM pricing in 2026. We are still more than 1.5 years away, while demand for AI is looking stronger. We will likely be looking at shortage in supply before we see any oversupply.

Total investment for M15X is KRW 20 trillion (USD 14.5bn), of which KRW 5.3 trillion will be for infrastructure. M15X equipment spending will be USD 10.7 billion, which is a meaningful addition to WFE in 2026 and 2027. Since M15X is for 1b nm and beyond, ASML’s EUV will be a part of this USD 10.7 billion spend. Yong-in cluster is still ready for mass production in 2H 2027, so this is an additional investment from SK Hynix.