I will explore how they work, how they differ and why it is important for investors watching the semiconductor sector.

For the earlier deep dive on HBM, please refer to the link below

Deep Dive on HBM - by Moore Morris and Ray Wang

1. The Memory Hierarchy

Not all memory inside a device works the same way. Some types are extremely fast but can only hold a tiny amount of data. Others are much slower but offer huge capacity.

A good way to think about it, is the Memory Hierarchy. The pyramid reflects trade-offs between speed, cost, and capacity:

• Fast memory is small and expensive (CPU Registers and Cache)

• Slow memory is large and affordable (NAND Flash, HDD)

Source: Avnet

At the very top, you have CPU registers which are tiny storage inside the CPU that operate at lightning speed. Just below that are caches like L1, L2, and L3 that rely on SRAM (Static Random Access Memory). Right below is DRAM (Dynamic Random Access Memory), which serves as the computer’s main working memory. This is followed by storage such as SSD (Solid State Drive) and HDD (Hard Disk Drive) that provide massive space at much slower speeds and lower costs. At the bottom of the pyramid is magnetic tapes, which is actually still in existence today. To illustrate the difference in speed, the access time difference between each level of memory is 10x from cache to DRAM and DRAM to SSD.

Source: GeeksforGeeks

2. How DRAM and NAND Work?

DRAM and NAND flash are both essential memory for modern electronics, but they serve very different purposes.

This is the key difference:

• DRAM is volatile as it loses all data when power is turned off

• NAND flash is non-volatile as it retains data even without power

Referring to the picture earlier, DRAM is Level 2 and NAND is Level 3 of the Memory Hierarchy respectively.

How DRAM Works

Every bit of information in DRAM is stored using 1 capacitor and 1 transistor. The capacitor holds an electrical charge to represent a “1” and no charge to represent a “0”. The transistor acts as a switch that connects the capacitor to the external circuit.

Source: Micron

However, capacitors aren’t perfect as they leak charge over time. This is why DRAM is called dynamic as they constantly need to refresh millions of times per second to maintain the data. But because it needs constant power, all data is lost instantly if the system shuts down. The benefit of DRAM is that it offers extremely fast access speeds, typically measured in nanoseconds.

How NAND Flash Works

NAND flash stores data by trapping electrons within the cell. This trapped charge changes the electrical properties of the cell, which can be detected later to read a “0” or “1.” This is known as the “NOT AND” operation.

Unlike DRAM, NAND does not need refreshing. It holds data even when power is removed, which makes it ideal for long-term storage. However, writing to NAND is slower and more complicated than writing to DRAM. You can't just flip a single bit as an entire blocks need to be erased before rewriting a new block. This means NAND is excellent for storage, but far less suitable as active working memory.

In early NAND designs, the standard structure was the floating gate. This involves the control gate that turns the cell on or off and the floating gate that stores the actual charge

Source: Micron

From Floating Gate to Charge Gate

Today, most of the 3D NANDs have adopted the charge gate technology. Charge trap NAND uses a silicon nitride layer to trap electrons instead of a floating gate. It’s a simpler and more scalable design, especially for 3D architectures.

• The trap layer is thinner and easier to fabricate in tall vertical stacks

• It reduces cell-to-cell interference which becomes a big issue in dense arrays

• It’s more robust over time as chips reach 100 layers and beyond

Source: The Memory Guy Blog

Source: Stored bits

From Planar to 3D Stacking

Originally, NAND cells were laid out flat and lined up side-by-side. This is known as Planar NAND. But as we approached the limits of how small each cell could get, manufacturers started stacking them vertically. In 3D NAND, the structure looks more like a skyscraper than a city block.

Source: Enterprise Storage Forum

Source: SK Hynix

Imagine hundreds of layers of memory cells stacked vertically and all connected through vertical channels etched through the entire stack. This shift to 3D NAND allows storage capacity to increase without shrinking cell dimensions further. More bits per wafer, lower cost and continued scaling can be achieved through stacking NAND cells. Instead of using expensive lithography tools from ASML for scaling, cheaper etching tools are used.

3. A Brief History of the Memory Industry (1960s–2020s)

The story of the memory industry is full of breakthroughs, competition and shifts in leadership. As with all emerging industries, it usually takes decades before a healthy state of competition is achieved with sufficient consolidation. In the case of DRAM, it was almost 40 years!

1960s: Birth of DRAM

The 1960s laid the groundwork for DRAM. At the time, most computers used magnetic core memory that is bulky, power-hungry, and expensive. Researchers were looking for a more compact and scalable solution. In 1966, IBM’s Robert Dennard invented the modern DRAM standard with 1 transistor per capacitor.

His breakthrough was simple but elegant: use a tiny capacitor to store charge (representing a “1” or “0”) and a transistor to read or write it. This invention set the stage for DRAM to become the dominant form of main memory in the coming decades, offering far higher density and lower cost than magnetic cores.

1970s: Commercial Launch of the DRAM Industry

The modern memory industry really started in the early 1970s as Intel launched the first commercial DRAM chip, the 1103, in 1970. It replaced bulky magnetic core memory and quickly became the standard for computers.

Throughout the 1970s, U.S. companies like Intel, Texas Instruments, and Mostek dominated DRAM manufacturing. Every few years, DRAM density quadrupled following a rough early form of Moore’s Law.

1980s: Japan Takes Over

The 1980s brought a major shift as Japanese firms such as NEC, Toshiba, Hitachi, and Fujitsu invested heavily in DRAM production. Their factories were more efficient, and their yield rates were 20-30% higher than the American rivals. This led to Japan controlling around 80% of the global DRAM market by the mid 1980s.

Source: Chips and Change

This led to intense price wars and lobbying from the U.S. memory producers. Eventually, the 1985 Plaza Accord was signed which led to a 50% appreciation of Japanese Yen over the next 2 years.

Source: Integrated Circuit Engineering Corp

Many U.S. companies simply exited the DRAM business as they were unable to compete. Then CEO of Intel Andy Grove led the company in a famous pivot away from memory and doubled down on microprocessors, changing its future forever. By the early 1990s, only a few U.S. companies are still involved in memory.

Meanwhile, a Toshiba engineer named Fujio Masuoka invented a new kind of memory called NAND flash in 1987.It wasn’t a big deal yet, but it would become the foundation for modern storage years later.

Source: Engineering and Technology History Wiki, photo of Fujio Masuoka

1990s: Korea Rises and NAND Grows

In the 1990s, another wave of competition arrived from South Korea. Samsung and Hyundai Electronics (later SK Hynix) aggressively built out memory fabs with strong government support. They focused on scaling and low costs, allowing them to start taking market share from Japan.

Meanwhile, NAND flash moved closer to reality. Samsung and Toshiba began producing early NAND chips at small density.

The seed of consolidation for the memory industry was planted near the end of the decade with the onset of Asia Financial Crisis in 1997. Under the pressure of the South Korea government, LG Semiconductor and Hyundai Electronics merged to become Hynix eventually. Elpida was formed in 1999 with the merger of the DRAM operation of NEC and Hitachi in Japan. Micron completed the acquisition of TI’s memory business in 1998.

At the end of the decade, big DRAM players remaining were Samsung, Hyundai, Micron, Elpida and Infineon.

2000s: The Flash Explosion

In the early 2000s, NAND flash demand exploded. Digital cameras, USB drives, and later smartphones needed a compact non-volatile storage solution.

Further consolidation in DRAM happened during the Great Financial Crisis. In 2008, Micron acquired 35.5% stake in Inotera, which is a JV of Qimonda (Infineon) and Nanya Tech. The next year, Qimonda filed for insolvency protection. 4 major DRAM companies remain: Samsung, Hynix, Micron and Elpida.

2010s: Start of the DRAM Oligopoly and the rise of 3D NAND

The DRAM downcycle in 2011 was the trigger of the final consolidation. In 2012, SK Telecom emerged as the sole bidder for Hynix for $3 billion and it was how Hynix became SK Hynix.

Elpida, Japan’s last hope in DRAM, eventually went bankrupt and was bought by Micron in 2013. In addition, Micron also bought out the remaining stakes in Inotera and acquired Rexchip (JV of Powerchip and Elpida).

An oligopoly emerged for the DRAM market as Samsung, SK Hynix, and Micron together controlled 90% of the market.

Source: DRAMeXchange

In NAND, Samsung led, but Toshiba, Western Digital, Micron, Intel, and SK Hynix kept the field highly competitive.

One huge technology shift changed everything: 3D NAND.

Instead of shrinking cells horizontally, manufacturers began stacking memory cells vertically. Starting with 24 layers, this became 48, 96, 200 and beyond. This solved the limits of planar scaling and dramatically increased storage capacity. By the late 2010s, 3D NAND had completely taken over the market.

2020s: HBM and China

Today, the memory landscape faces new forces as China is trying to build its own memory industry. Companies like YMTC and CXMT have started shipping competitive NAND and DRAM products respectively. They’re still behind leaders like Samsung and Micron in technology, but they’re moving fast.

At the same time, memory remains highly cyclical as always. After the memory “supercycle” in 2017-18, another bust hit in 2019. Another sharp downturn came in 2022.

The rise of AI and HPC has fueled demand for specialized memories such as HBM (High Bandwidth Memory).

4. The Current Competitive Landscape

Today, the memory business isn’t crowded as it is mostly controlled by a handful of giants. This was a huge contrast to the 1980s where almost every semiconductor companies globally produced memory chip.

DRAM

Three companies dominate the DRAM market: Samsung (South Korea), SK Hynix (South Korea) and Micron Technology (U.S.). Together, they control about 95% of the world’s DRAM revenue.

For more than 3 decades, Samsung led in market share and technology leadership. Samsung’s strong balance sheet, diversified businesses and cost leadership allow them to weather through all the previous downcycle. However, no one in the industry ever expects Samsung to lose its position as market leader in 2025.

In Q1 2025, SK Hynix is the new market leader with more than 36% revenue share of the DRAM industry. This is achieved through its dominant market share in AI-fueled HBM demand and a declining DRAM spot price. The price of an HBM chip is 5 to 10x more expensive than DDR5 on a per bit basis.

Source: Counterpoint

Micron is the up-and-coming player with a better yield rate in HBM than Samsung. Historically, the company has done best in capital allocation by acquiring capacity for cheap during the downcycle.

Ever since the acquisition of Elpida in 2013, the industry’s return on capital has improved tremendously. These days, it is common to see DRAM companies commenting on production cut or capacity upgrade during DRAM downcycle. While it remains cyclical as always, the 3 companies are now earning a through-cycle return above the cost of capital. True return for the DRAM operation is likely higher than the figures below as the 3 companies have NAND businesses. An investment in the memory companies at below book value is likely to pay off.

Source: Nomad Semi

Source: Micron

NAND

Unfortunately, the NAND industry is not as profitable as DRAM although it is just 1 consolidation away.

The NAND flash is still an oligopoly, but with 5 different companies

1. Samsung

2. Kioxia (spun out of Toshiba)

3. Sandisk (spun out of Western Digital, partner of Kioxia)

4. SK Hynix

5. Micron

Source: Trendforce

Samsung is still the leader in NAND although the cost advantage is narrowing.

In 2021, SK Hynix acquired the Solidigm operation from Intel as then-CEO Pat Gelsinger wanted to raise money to fund the foundry business. The combined business made SK Hynix the 2nd largest company in NAND.

That merger sparked speculation on whether the Micron or Western Digital will make a move to avoid being left behind. Without further acquisition, Micron will be uncompetitive in NAND as its market share today is only 12%.

Kioxia and Sandisk enjoyed a unique partnership through their joint venture. Kioxia controls 100% of the fabs and operation of the NAND business. Through the JV, Kioxia and Sandisk split the output as well as the cost of capital expenditure & R&D. Wafer output from Kioxia operation is split 50-50 between Kioxia and Sandisk.

Source: Sandisk

Both Kioxia and Sandisk are the weakest player in the industry as they do not have a profitable DRAM business to fund them through the cycle. They have been losing market share to Samsung and SK Hynix over time. The first step for a merger between Kioxia and Sandisk has been taken through the IPO of Kioxia and spin-off of Sandisk.

Without a profitable business to finance them through the cycle, Kioxia is increasingly facing the stress of increasing capacity. Well-known activist investment firm Elliot was the one who pushed Western Digital to spin-off Sandisk. Meanwhile, Kioxia is controlled by Bain Capital in a consortium that includes SK Hynix. SK Hynix had previously rejected the merger deal as they claimed the deal undervalued their investment in Kioxia.

The Rise of China Memory Competition

China doesn’t want to rely on foreign memory makers and has been making efforts in domestic substitution. Two key players have emerged with CXMT (ChangXin Memory Technologies) in DRAM and YMTC (Yangtze Memory Technologies) in NAND.

Back in 2016, there were 2 main companies (Fujian Jinhua Integrated Circuit and Innotron) focusing on DRAM production in China. In 2018, Fujian Jinhua was put on the U.S. BIS Entity List, which meant it could no longer buy semiconductor equipment with U.S. technology. In a separate lawsuit, Micron sued Fujian Jinhua and UMC for stealing its memory IP.

The other company was Innotron, which was based in Hefei. Innotron was established in 2017 as a JV between Hefei government and China Integrated Circuit Industry Investment Fund. In 2019, Innotron changed its name to CXMT.

To avoid similar lawsuit as Jinhua, CXMT licensed its IP from Qimonda and Rambus. CXMT started producing DRAM around 2020 and has been growing its capacity rapidly since 2023.

There are concerns whether CXMT’s rapid capacity growth will be a threat to the oligopolistic nature of the DRAM market. By the end of 2025, it is estimated that CXMT will achieve a capacity of 300k wpm. This will be equivalent to 15% of the global DRAM capacity. Backed by Chinese government subsidies, CXMT has also started to sell DDR4 more actively to the Chinese smartphone OEMs. This was one of the concerns raised when memory prices took a turn last year.

However, the good thing is CXMT is still behind the main DRAM companies in terms of technology. At 16nm, CXMT is closer to 1z nm. For reference, both Samsung and Hynix are working on mass production of 1c nm at the end of the year. By process technology, the DRAM oligopoly is still 3 generations ahead of CXMT (1z → 1a → 1b → 1c nm).

According to Techinsight, CXMT latest 16nm chip has a bit density of 0.239Gb per mm square. This is 40% lower bit density than the average of 0.4-0.45Gb per mm square achieved by the DRAM oligopoly. As a result of the 40% lower bit density, the actual bit market share of CXMT is around 5-6% despite having 15% of global capacity share. Right now, CXMT is still mostly shipping DDR4 products rather than the DDR5 products from the global companies.

Another issue that CXMT faces is its ability to continue to migrate to the next process technology. In the latest restriction, the U.S. government has further restricted equipment access for DRAM production from a threshold of bit density of > 0.288Gb / mm square to a bit density of >0.20Gb / mm square. This was a loophole that had allowed CXMT to produce at 1z nm despite the 18nm restriction for DRAM.

The other major player is China’s leading NAND producer YMTC, which has a competitive 3D NAND product. Founded in 2016 under the Tsinghua Unigroup umbrella, YMTC had received billions in funding.

Unlike many Chinese semiconductor firms, YMTC didn’t aim to merely replicate existing technologies. It created an independent path by coming out with a novel proprietary NAND flash architecture called Xtacking in 2018. Instead of fabricating the memory cell array and the peripheral logic circuitry on the same wafer, YMTC builds them separately and then bonds them together. This is achieved through a wafer-to-wafer hybrid bonder.

Source: Semiconductor Digest

As the logic and memory layers are fabricated and optimized independently, this enables a much faster read and write speeds. By offloading logic to a separate wafer, better die area efficiency is achieved as the memory array can be more densely packed. Despite the limitation of equipment access, YMTC is able to achieve a bit density nearly on par with the global giants.

Source: Techinsights

In an endorsement of Xtacking architecture, Kioxia had announced the adoption of a similar CMOS directly Bonded to Array for their 8th Gen BiCS Flash. SK Hynix is also exploring a similar technology roadmap at the moment. This is great news for wafer-to-wafer hybrid bonder providers such as EV Group and Tokyo Electron.

Source: Kioxia

Unlike CXMT, YMTC has more success due to its independent technology roadmap. Not only is it suppling entry level SSD products, it is also supplying enterprise grade SSD. By NAND bit share, YMTC should have a market share of 7-8% in 2024.

Despite the great success enjoyed by YMTC in its memory technology innovation, the firm was placed on the Entity List in December 2022. This restricts U.S. firms from supplying to YMTC without a license. Key vendors like LAM Research, Applied Materials and KLA were forced to halt shipments of essential tools. This led to a stalled 232L 3D NAND roadmap and slower capacity expansion.

However, not all is lost as China’s domestic supply chain is working hard to provide the key semiconductor equipment. In particular, AMEC plays an important role in delivering high aspect ratio etching machine as this is essential for 3D stacking in NAND. AMEC is able to achieve a 60:1 aspect ratio with their CCP etching tool and is aiming to achieve 90:1 aspect ratio next. According to Kokusai, YMTC is starting to accelerate its capacity plan again this year and is aiming for production of 200-300L 3D NAND.

Given the huge market in China, it is inevitable that both CXMT and YMTC will increase their bit share going forward. It is critical to track their progress as they could threaten the current oligopoly status of the global memory market.

5. How DRAM and NAND Are Scaling Today

For years, memory chips got better mainly by shrinking as smaller cells meant more bits per wafer, lower costs and better performance. But that simple formula started running into hard limits.

Now, both DRAM and NAND have taken on new scaling paths.

DRAM Scaling

DRAM scaling has always been tricky. Every DRAM cell needs a capacitor to store charge and that capacitor has to hold enough electrons to tell a "1" from a "0".

As cells got smaller, it became harder to build capacitors with enough storage. At the same time, wires got narrower, increasing resistance and slowing things down.

Source: Micron

In the past, DRAM density doubled roughly every 2–3 years. From 2000 to 2010, DRAM node sizes shrank from 180nm to 40nm, which is a 4x density increase in a decade. Since 2015, node shrink has become incrementally slower from 28 nm to 1c nm today. These days, node migration only delivers 10 to 15% in density gain per generation. One benefit of the slower node shrink is that it is harder for memory companies to increase supply without incremental greenfield capex. Supply is much more predictable.

Source: Citi

To deal with this, DRAM makers like Samsung, SK Hynix, and Micron have adopted EUV on their newest nodes. EUV helps to pattern finer features without the need for multi-patterning. Both Samsung and SK Hynix have adopted EUV at 1a nm, and are increasing EUV layers count as they progress towards 1b and 1c nm. Micron will be introducing EUV at 1-gamma at its Hiroshima plant.

Beyond the next generation 1d nm, there is visibility to the future DRAM scaling roadmap. DRAM will transition from 6F² to 4F², before it migrate to 3D DRAM in 2030s.

Source: Tokyo Electron

4F² refers to the dimension of a single DRAM cell at 2F x 2F, where F is the minimum feature size of the manufacturing process. This is the smallest possible DRAM cell size. Both Samsung and SK Hynix will adopt 4F² as they migrate into <10nm. Samsung has called it Vertical Channel Transistor (VCT), while SK Hynix has named it Vertical Gate (VG).

Source: Samsung

The new 4F² design reduces the footprint of each memory cell by approximately 30% compared to the older 6F² layout while maintaining the same lithography node. This is due to a more compact structure through stacking the drain, channel, source and capacitor vertically. This approach not only increases cell density, but also improves power efficiency. Cost saving is also achieved from savings in lithography cost.

Source: Samsung

Source: SK Hynix

The next evolution will be 3D DRAM where memory cells are now stacked vertically within the chip. Samsung has called its 3D DRAM technology as Vertically Stacked Cell Array Transistors (VS-CAT) or (VS-DRAM).

While 3D DRAM is still years away, it will reduce litho intensity significantly. On the other hand, 4F² may maintain or reduce the litho intensity. Key beneficiaries will be current etching and deposition equipment providers such as Lam Research, Tokyo Electron and ASMI. 3D DRAM is much more complicated than 3D NAND stacking, so the exact implementation timeline remains uncertain.

NAND Scaling

Source: Sandisk

The 1st scaling method is lateral scaling which is packing more bits per memory layer. However, this is really difficult as density increase leads to higher cost, cell to cell interference and impact data retention.

NAND flash found a better way forward through stacking layers known as 3D NAND. Instead of shrinking cells further, engineers started building memory cells on top of each other. Samsung was first to market with 24L 3D NAND back in 2013. Now, leading chipmakers have produced over 200 layers 3D NAND with 300+ layers coming soon.

Source: SK Hynix

More layers = more storage without shrinking the cells too much. Horizontal pitch shrinking has taken a pause since the advent of 3D NAND. It solves a lot of scaling headaches although building tall stacks brings its own challenges that has to be solved by better etching tools.

Source: Micron

For now, the roadmap is clear, which is to continue stacking up to 1000 layers by 2030. Previously, we have done a deep dive on Tokyo Electron whose cryogenic etching will be a key technology to achieve high aspect ratio etching for 1000 layers 3D NAND.

Source: Tokyo Electron

Another method is logical scaling, which involves squeezing even more bits into each cell. Originally, each cell holds a single bit, also known as SLC (Single-Level Cell). But manufacturers realized that by precisely controlling charge levels, they could store more bits per cell:

• 2 bits per cell → MLC (Multi-Level Cell)

• 3 bits per cell → TLC (Triple-Level Cell, now the mainstream)

• 4 bits per cell → QLC (Quad-Level Cell, growing in adoption)

• 5 bits per cell → PLC (Penta-Level Cell)

Bits per Cell: SLC → MLC → TLC → QLC → PLC

While more bits per cell can reduce cost, it also slows down write speeds and lower endurance since reading and writing becomes more sensitive to voltage shifts and noise. That’s why high-end SSDs still use SLC or TLC, while QLC and PLC target cold storage or low-write applications. Logical scaling gain is also getting lower as it is only 25% gain moving from QLC to PLC.

The last method is architecture scaling in a method similar to the Xtacking architecture that YMTC has adopted. SK Hynix is also considering 4D NAND, which uses hybrid bonding to stack the memory cell on top of the peripheral circuit.

6. Memory Market and Demand

Few years ago, the DRAM market is equally split between PC, mobile and data center. After Generative AI demand took off in 2023, it is now a major new driver of DRAM demand. Higher DRAM bandwidth is required to prevent bottleneck during AI training and inferencing. With the rapid growth in AI, data center will account for 2/3 of the DRAM bit demand in 2029. Assuming a single digit annual decline in DRAM ASP and high teens bit demand growth, the DRAM market is expected to grow at mid to high single digit over the next few years.

Source: Yole

NAND demand has slowed down from the high 30s during the 2010-20 decade and we are looking at high teens bit demand growth going forward.

Source: Sandisk

7. Other Memory Technologies to Watch

While DRAM and NAND rule today, a few emerging technologies could shake things up down the road.

The most important is HBM which is very important for AI today. I have written a deep dive on HBM last month, do check it out.

Deep Dive on HBM

Here are some others to keep an eye on:

• MRAM (Magnetoresistive RAM):
  Uses magnetic states to store data. It is super fast, non-volatile, and durable.
  Might replace some embedded SRAM or flash in future chips.

• ReRAM (Resistive RAM):
  Stores bits by changing the resistance of materials.
  Could offer speed between DRAM and NAND, which makes it a good fit for storage-class memory someday.

• FeRAM (Ferroelectric RAM):
  Uses polarized electric fields.
  Very low power, extremely durable.

• CXL (Compute Express Link) Memory:
  Not a new memory type, but a new way to connect memory.
  CXL lets servers tap into memory pools outside the CPU, improving flexibility and utilization.

None of these will replace DRAM or NAND anytime soon given cost consideration and maturity. But they could carve out important niches and some might reshape how memory is used altogether.

8. Conclusion

Memory demand outlook has improved significantly over the last few months with recent AI developments. For DRAM, NVIDIA’s Rubin CPX will feature 128GB GDDR7, while SOCAMM2 in Rubin Vera CPU will feature 3x the DRAM content of Blackwell Grace CPU. HBM content is also expected to receive a huge boost from 228GB in Rubin to 1024GB in Rubin Ultra.

Storage demand has also surged on the back of strong demand from the hyperscalers. With HDDs supplies unable to keep up, demand has spilled over into SSDs. Both HDD and NAND suppliers have been conservative in capacity expansion in recent years, suggesting that the current shortage could persist for much longer.

Microsoft’s 5 football fields length storage systems at Wisconsin AI datacenter

This will be my last post for a while, as I’ll be stepping back to focus on family commitments. Thank you for reading and supporting my work as it has been a privilege to share my thoughts with you. I look forward to returning some day in the future.

Taiwan’s exchange-traded fund (ETF) market has exploded as total ETF assets jumped 55% YoY to USD 196 billion in 2024 and now account for about 2/3 of all onshore fund assets. According to Financial Times, ETFs only accounted for 27.5% and 56.7% of the public fund industry assets in 2018 and 2023 respectively.

It is important to understand the ETFs given the sizable impact they can have on the market. An example will be the deletion of MediaTek from Capital Tip Customized Taiwan Select High Dividend ETF (00919 TW) last week. MediaTek was a 9.67% holding in the 00919 ETF but was deleted from the index on 4th June 2025. 00919 had to sell 27 million shares of MediaTek or close to 2% of total outstanding shares of MediaTek.

Source: Nomad Semi

This creates an opportunity for buyers as the ETF is a forced seller regardless of fundamentals or fair valuation. MediaTek underperformed the market by 4% from 4th to 5th June before the ETF selling pressure eased off subsequently. If you had bought at the bottom on 5th June, you would have made 8% in just 4 trading days.

Source: Google Finance

The Rise of High Yield ETF

The ETF market in Taiwan boomed last year with the popularity of the high dividend yield ETFs. Notably, there are 5 big high yield ETFs which have a total asset of NTD 1.57 trillion or USD 52 billion. The combined AUM of these 5 high yield ETFs is 2.5x bigger than the flagship Taiwan Top 50 ETF which is based on the Taiwan 50 Index. They also rank among the most traded securities every day.

Source: Nomad Semi

To get a sense of how popular they are, we can also look at the total number of shareholders for the ETFs. Taiwan stock market has 13 million investors, of which 1.75 million owns Cathay Taiwan ESG Sustainability High Yield ETF and 1.47 million owns Yuanta/P-shares Taiwan Dividend Plus ETF. This is just a little below the 1.79 million shareholders for TSMC.

Source: TDDC

1 unique feature of these high yield ETFs is that they do not own TSMC, which is 56% of the Taiwan 50 Index and close to 40% of total Taiwan market capitalization. Many retail investors already own TSMC shares (1.75 million local investors) or through the Taiwan Top 50 ETF.

These ETFs offer retail investors non-TSMC exposure in Taiwan with a high dividend yield. The 3 most popular high yield ETFs are Yuanta/P-shares Taiwan Dividend Plus ETF, Cathay Taiwan ESG Sustainability High Yield ETF and Capital TIP Taiwan Select High Dividend ETF. These 3 high yield ETFs with a combined AUM of USD 42.5 billion offer quarterly distribution with an annual dividend yield of more than 10%. While Fuh Hwa Taiwan Technology Dividend Highlight ETF and Yuanta Taiwan Value High Dividend ETF dividend yield is much lower than the former 3, they offer monthly distribution payout.

High Payout Ratio in Taiwan

Taiwan companies often have high payout ratio regardless of whether the companies are in the semiconductor, financials, retail or traditional industry.

Source: TWSE

There are multiple reasons for these shareholder friendly actions. The most important reason is Taiwan’s addition 5% profit retention tax on any earnings not distributed by the end of the following year. This creates a healthy hurdle rate for Taiwanese companies when evaluating whether they should distribute excess cash as dividend or to keep them on balance sheet or for expansion opportunities. In addition, Taiwanese companies often have healthy balance sheet and stable cash flow without the need to frequently access the capital market (ODMs didn’t used to have to raise money). Insurance companies are also significant source of domestic institutional funds.

Stock Selection Methodology

To understand how they decide on inclusion and deletion, we can look at the methodology for Yuanta Taiwan Dividend Plus ETF.

1. The universe starts from the top 150 stocks in Taiwan (Taiwan 50 and Taiwan Mid-Cap 100 Index)

2. The market cap is then adjusted for to ensure it meets 5% free float requirement, which is what they deemed to be available for public trading. Government, founder, family, management and strategic investors holdings are often excluded from free float

3. The Index then takes the top 50 stocks ranked by their next 12 months forecasted cash dividend yield. The forecast is taken from Institutional Brokers Estimate System and relies on forward estimates.

4. Semi-annual reconstitution is done in June and December. A limit is placed such that no single name is more than 6% of the Index or that the Index will own more than 15% of the investable market cap.

Source: Yuanta

How Significant are They?

The reason why I wrote this article is that these high yield ETFs are becoming major market movers. The AUM of these 5 high yield ETFs accounts for 3.6% of the total non-TSMC market capitalization in Taiwan. At the individual stock level, they often pose much higher concentration risk given they only hold 30-50 stocks.

In particular, they account for close to 20% of total share outstandings of certain semiconductor stocks such as UMC, Vanguard and Novatek. All 5 high yield ETFs own UMC due to its attractive 6% dividend yield. The NTD 107.5 billion holdings in UMC is equivalent to 18.5% of UMC’s total market capitalization.

For Vanguard International Semiconductor, 3 ETFs own 17% of Vanguard’s total market capitalization. The influence of ETFs is even more significant for Vanguard considering that TSMC owns 27% and National Development Fund owns 16% of the company. This implies that 3 ETFs own 1/3 of the available free float and that any deletion decision will be executed within a week. Share price of both companies will also be influenced by inflow and outflow of the AUM of these ETFs.

Another implication of the high yield ETFs is that there is certain downside support for any high dividend yield stocks in Taiwan. As share price falls and dividend coupon is fixed, dividend yield will go up which could lead to inclusion in the index and ETFs. Conversely, when shares get expensive the ETFs could remove the company from the index.

Conclusion

While Taiwan’s dividend ETF craze has democratized access, it has also rewired the market micro-structure and shifted price discovery from fundamental research to rulebooks. For semiconductor investors in Taiwan, understanding where passive flow goes and reverses can provide tactical allocation edge. Stay nimble and never forget that these ETFs can both distort and support the valuation of the underlying stocks.

You will hear a lot about HBM these days, especially if you follow AI chips. HBM stands for High Bandwidth Memory. It’s a special kind of DRAM, stacked vertically and connected to processors through tiny wires inside the silicon called TSVs (through-silicon vias). TSV allows the direct connection of multiple HBM DRAM dies to increase overall memory bandwidth.

Source: Blocks and Files

Why is HBM important?

Here’s the key advantages of HBM:

• High speed: HBM delivers terabytes per second which is more than 20x faster than regular DDR memory

• Power efficiency: Because it’s right next to the logic die, energy is saved since data doesn’t have to travel far

• Area efficiency: Delivers highest capacity per unit area

Source: SK Hynix

Memory bandwidth is important in the era of Generative AI as model training is often bandwidth constrained rather than compute constrained. The attention mechanism in transformer model has to store and calculate the relationship between all the tokens. Memory requirement is quadratic in proportion to the sequence length. Similarly, memory is also a bigger constraint during inference, due to the need to handle longer context windows and enlarged key‑value cache (KV cache) in the transformer model. Memory consumption for KV cache grows linearly with the token size.

Source: Attention is all you need (2017)

Source: Positron AI

HBM Technology

With each generation of AI chip, an upgrade in HBM is a key factor for better performances (higher bandwidth or capacity). In a tick-tock cycle, the main upgrade for NVIDIA GPU in its 2nd generation of the same architecture will be the HBM capacity. 50% jump in HBM capacity from H100 to H200, B200 to B300 and 4x jump from Rubin to Rubin Ultra.

This is in the form of either having more HBM stacks per GPU module, higher number of DRAM dies per HBM module or upgraded HBM generation. HBM4 achieves higher bandwidth by doubling the number of channels per stack from 8 to 16 and a significantly faster I/O per pin.

Source: SK Hynix

Given the increase in HBM content with GPU and ASICs going forward, the HBM market is expected to grow rapidly. According to SK Hynix, the HBM industry is forecasted to grow at a 50% CAGR from 2024 to 2028. For the DRAM producers, HBM has proven to be less cyclical than traditional DRAM. While volume may still fluctuate in the future, HBM contract pricing is agreed 1 year in advance. This is better than the shorter contract or even spot pricing for DRAM.

Source: Yole

SK Hynix is the current winner of HBM race

SK Hynix is the winner of the HBM race thus far with its superior MR-MUF (Mass Reflow Molded Underfill) technology. Both Samsung and Micron have chosen the inferior TC-NCF (Thermal Compression with Non-Conductive Film) roadmap. This led to SK Hynix dominating the HBM market with more than 60% market share. This is mainly because SK Hynix serves as Nvidia’s primary HBM supplier for its high end GPU from Hopper to latest Blackwell GPUs (e.g. GB200). Notably, Nvidia accounted for over 60% of global HBM consumption in 2024 and is estimated to account for over 70% in 2025, according to Morgan Stanley.

Source: Samsung Securities

MR-MUF is better than TC-NCF due to better thermal dissipation and higher yield rate. MR-MUF has an average yield rate that is 20% higher than TC-NCF. Thermal dissipation is becoming more important as the number of HBM layers increases over time. More HBM dies stacked together in an area generates more heat. As MR-MUF has 3x the number of thermal bumps than TC-NCF, heat dissipation is much better and HBM can remain at a lower temperature.

Source: SK Hynix

Another feature of MR-MUF is that the process is done at room temperature and with small force, while TC-NCF is done at high temperature of 300⁰C and strong force. High temperature creates potential warpage issues where the layer will become bent. Strong force also has the potential to damage chips during the stacking process.

Source: SK Hynix

SK Hynix also has an exclusive epoxy molding compound that enables more uniform gap filling and better encapsulation. It reduces voids, enhances heat dissipation and minimizes warpage. The resin-based insulation material is provided through an exclusive contract with a key Japanese supplier called Namics Corporation for many years. This is a key reason why Samsung and Micron are unable to replicate the MR-MUF technology in addition to the patent barrier. With TC-NCF’s film-based underfill, there are tighter alignment tolerances and struggle with flow consistency that gets worse with higher stacks.

Source: SK Hynix

One reason why Samsung has struggled so much is because of their front-end technology. Given that both Samsung and Micron are using TC-NCF, the back-end technology is not the reason why Samsung has yet to be qualified by NVIDIA. Since 1a nm, Samsung had started to struggle with its front-end process. Some attributed it to cultural and management issues, while others said it was due to an aggressive scaling roadmap. Front-end yield rate is particularly important in HBM as the number of HBM dies stacked will continue to grow from 8-Hi to 16-Hi. With a 95% yield rate, the final yield rate will be 66% for 8-Hi and 44% for 16-Hi.

As a result, Samsung is now using 1c nm DRAM die and 4nm logic die for HBM 4 in an attempt to catch up to peers. However, the result for Samsung’s 1c nm is not satisfactory whereas rival SK Hynix had already achieved impressive yield with 1c nm. Note that SK Hynix will be using their mature 1b nm technology for HBM4 given their superior yield rate. Without success at 1c nm development, Samsung is likely to fall further behind in both DRAM and HBM. Unless yield rate at 1c nm can mature in time to more than 90%, it is unlikely for Samsung to catch up to SK Hynix at HBM4. In addition,

Source: Digitimes

Another key factor should also be factored in the HBM4 race is the migration of the base die from a planar DRAM process to an advanced FinFET logic node.

By moving the base die to logic process technology, it allows the base die to have lower power consumption, boosts transitions performance and gives flexibility for customer-specific features. With FinFET process technology, it turns the base die into a customizable chiplet that provides higher performance with better energy efficiency (especially using more advanced nodes although it's more pricey) while giving memory vendors flexibility to serve hyperscale and accelerator customers for specific purposes.

Source: Joongang Daily

Given such change, Samsung is expected to fabricate this base die in‑house on its own advanced node by reportedly Samsung Foundry’s 4nm process node while industry reports suggest SK Hynix and Micron will outsource theirs to TSMC, likely on 3 nm for customized base die.

The base die for HBM4 essentially has three main functions:

• Controlling DRAM Stacks: It serves as the control plane for the entire HBM stack, handling all read/write, refresh, and repair operations across the vertically stacked DRAM layers above it.

• Managing the I/O interfaces and Data Transfer: The base die of HBM4 will host  2048‑bit physical layer I/O (JEDEC Standard), which is twice that of HBM3E, and clock network that move data between the memory stack and the host processor in either GPU or ASIC.

• Integrating Logic Chips & Customizing HBM4. Since the based die will be fabricated in logic processes (e.g., 4 nm Samsung, 3/12 nm TSMC), it creates room for on‑die power management, ECC (Error‑Correcting Code), and customer‑specific accelerators. With the use of a logic in base die, it also enables “custom HBM” variants and supports advanced 2.5D/3D packaging road maps depending on customer demand for specific workload.

Source: Alphawave Semi

With that in mind, it is clear that the quality of HBM base die are emerging as another key battleground among memory vendors, who increasingly tailor these logic layers to meet customer‑specific power and performance targets for upcoming HBM4. TSMC’s N3 family has demonstrated robust capability and stability over the past three years, so process quality should pose little concern for SK Hynix or Micron.

The key strategic question is whether moving to 3 nm despite its higher wafer cost delivers a tangible performance benefit versus staying on a less advanced node, such as N5 or even N12. Samsung faces a different calculus. Its 4 nm track record remains controversial, and earlier 4 nm-based products have attracted industry criticism. Before HBM4 ramps, Samsung must validate that its in‑house 4 nm process can deliver competitive base‑die quality in comparison to its competitors. If not, it risks falling further behind Micron and SK Hynix, who will leverage TSMC’s proven logic technology, even if Samsung retains a nominal cost advantage by remaining fully integrated.

Beyond its superior role in bonding technology and the company's competitive DRAM manufacturing, SK Hynix’s leading role in HBM stems from the company's consistent investment in HBM technology and talent for more than a decade. Since 2013, SK Hynix has consistently invested in HBM technology with its first HBM co-developed with AMD. Early, sustained investment has kept SK Hynix at the forefront of HBM innovation—beginning with HBM2 in 2017, advancing to HBM2E in 2019 and HBM3 in 2021, and culminating in today’s industry‑leading HBM3E and forthcoming HBM4 products.

This first-mover and consistent drive in HBM turned out to be extremely critical for SK Hynix’s success in HBM given the complex manufacturing process required as well as the technical learning curve for the professionals. More importantly, it has enabled the company to continuously identify and align with optimal supply chain partners that match its technology roadmap without disruption.

In contrast to SK Hynix’s steady commitment, Samsung’s engagement with HBM has been rather sporadic. Despite Samsung has kept pace with SK Hynix in HBM in most of 2010s with its first‑generation HBM and HBM2, the firm decided to dismantle its HBM team in 2019, citing the limited market potential of HBM. This was a move that likely stalled technical progress and, more damagingly, severed the talent pipeline needed for future HBM development in coming years. In hindsight, the decision is clearly a significant strategic misstep by Samsung.

More importantly, the timing is proven fatal as the team was dissolved only about three years before the AI boom driven by launch of ChatGPT-3, which is the key period of time for companies to gear up developing the key HBM to power the AI chips, such as HBM3 and HBM3E, which later powered Nvidia’s most popular and widely adopted H100.

Samsung’s strategic retreat from HBM also coincided with SK Hynix’s technological breakthrough in HBM. It was exactly in 2019 when SK Hynix unveiled its MR-MUF bonding technologies, as previously noted, the key technology that helped the firm's HBM products stand out from the competition with Micron and Samsung.

Source: SK Hynix

Hybrid Bonding is a game-changer for HBM

As a result of the superior MR-MUF technology, SK Hynix has dominated the HBM market. However, the leadership position is susceptible to change if hybrid bonding is adopted for HBM. As hybrid bonding is a new technology, whichever player first mastered it will have an advantage in the learning curve.

In hybrid bonding for HBM, the process begins with surface preparation of the die to be bonded, creating planarized copper pads and surrounding dielectric layers. These surfaces are then chemically treated and activated to ensure high-quality adhesion. Next, the dies are precisely aligned and directly bonded to form both a copper-to-copper connection and a dielectric-to-dielectric mechanical bond. Once bonded, the stack undergoes low-temperature annealing (typically <400°C) to strengthen the interconnects.

Source: IEEE Spectrum

Hybrid bonding enables direct Cu-to-Cu (copper-to-copper) bonding between stacked dies without the use of micro-bump. This solution offers much tighter pitch, lower resistance and better thermal characteristics. Hybrid bonding supports below 10μm pitch (vs ~40-55μm for microbumps), allowing many more connections between layers. With a tighter bump pitch and no gap between HBM dies, the overall stack height of HBM can also be reduced.

Source: Samsung

Initially, JEDEC had specified a package height of 720um for HBM. This was possible to achieve for both 8-Hi and 12-Hi HBM3/3E using both MR-MUF and TC-NCF. As we move to 16-Hi HBM4, hybrid bonding was supposed to be an inevitable technology requirement to meet the 720um height. With some lobbying, JEDEC relaxed the package height to 775um for HBM4. This allows the usage of both MR-MUF and TC-NCF for HBM4. Other than reducing overall stack height, hybrid bonding improves overall power and bandwidth through higher density and shorter connection between the dies.

Source: SK Hynix

Source: Besi

The main reason why hybrid bonding is not yet adopted for HBM is that it costs a lot more than the current method. Hybrid bonder costs USD 3 million as compared to USD 1-2 million for TCB.

In addition, the total cost of ownership is much higher due to additional CMP (Chemical Mechanical Planarization) steps and the requirement for higher-class cleanrooms. CMP is needed to ensure both dies are smooth and flat at the bonding interface. As a result of the cleanroom requirement, other tools such as grinder, dicer and die placement will become more expensive as they have to meet front-end specifications. Hybrid bonding is also where the line of front-end and back-end gets a little blur.

While Samsung and Micron will try to get ahead of SK Hynix with hybrid bonding, the timeline for hybrid bonding mass adoption is likely to be in 2028 or 2029 for HBM5 20-Hi. This is also in line with NVIDIA’s roadmap where we will see HBM5 adoption only in late 2028 at the earliest to be paired with the next generation of GPU after Rubin Ultra.

We can also deduce from the volume production date of the 2 new advanced packaging facilities that Micron and SK Hynix had invested in. Micron broke ground on a $7 billion HBM advanced packaging facility in Singapore in 2025 with mass production expected in 2027. SK Hynix plans to invest $3.87 billion in their new Indiana advanced packaging plant which will start production in 2028.

Source: SK Hynix

HBM Equipment Suppliers

There are a few key equipment suppliers for the HBM market

1. Thermal Compression Bonder (TCB): Hanmi, Hanwha, ASMPT, Kulicke & Soffa, Semes

2. C2W Hybrid Bonder: Besi, ASMPT, SUSS Microtec

3. Metrology: Camtek, KLA

4. Molding: ASMPT, Besi, Towa

5. Grinder: Disco

6. CMP: Applied Materials, Ebara

7. Temporary Bonder, Debonder: SUSS Microtec, Tokyo Electron

8. Tester: Advantest, Teradyne

9. TSV: Applied Material, LAM Research, Tokyo Electron

Within the supply chain, TCB and Hybrid Bonder receive the most attention due to the intense competition landscape. Bonder tools are also required to stack the HBM dies on top of each other.

TCB is currently the mainstream bonder equipment used by SK Hynix, Samsung and Micron. TCB market for HBM packaging is currently led by Korean firms like Hanmi Semiconductor and Hanwha Precision, both of which supply to major DRAM makers like SK Hynix and Micron. Hanmi is especially dominant in HBM3 and HBM3E with its superior cost-performance and productivity. The company has been the top supplier for SK Hynix till today despite some of the disputes that they have. Hanmi is also the main supplier of TCB to Micron and the Chinese producers.

While ASMPT and KLIC (Kulicke & Soffa) are also active in the TCB market, their historical strength has been more on logic packaging. Precision level is higher in logic than HBM packaging, which justifies the higher cost of their machines.

The C2W (Chip-to-Wafer) hybrid bonder market for HBM is still in its early stages but rapidly becoming a key battleground. The industry is transitioning from microbump-based TCB to bump-less Cu-to-Cu hybrid bonding for HBM5 and beyond. While TCB vendors may attempt to evolve into hybrid bonding, they require partnership with front-end equipment producers. To this end, Besi has partnered with Applied Materials and ASMPT has partnered with EV Group. Applied Materials have contributed their expertise in etching, CMP, deposition, cleaning, metrology and inspection to the partnership. For those who are not familiar with EV Group, this company is the undisputed market leader in Wafer-to-Wafer permanent bonder. Korean vendors such as Hanmi and Hanwha are also exploring hybrid bonding extensions of their TCB platforms, but they currently lack the precision and low-temperature process control.

Currently, Besi is leading in the hybrid bonder race with the current 100nm accuracy hybrid bonder and upcoming launch of Generation 2 50nm precision hybrid bonder that achieves bump pitch of <4 um. For both ASMPT and KLIC, they are trying to delay the adoption of hybrid bonder with their next generation fluxless TCB tool (AOR TCB by ASMPT, APTURA™ FTC by KLIC) that allows placement accuracy of sub-1 um and <10um bump pitch.

Source: Besi

Source: ASMPT (AOR TCB)

China’s Catch Up in HBM

China’s progress in HBM remains limited in comparison to three top memory makers and poses little immediate concern for them, especially when the memory development in China is under the shackle of the U.S.-led restrictions on semiconductor manufacturing equipment, including lithography, etching, TSV, and etc. However, China has a proven track record of rapidly advancing its memory technologies despite regulatory challenges, as demonstrated by two leading memory makers CXMT and YMTC in recent years.

In particular, CXMT, founded in 2016, has been the DRAM leader in China and has advanced rapidly in the traditional DRAM area over the past few years, challenging the three memory giants marketplace in mid to low-end DRAM (e.g. DDR3 and DDR4). Besides, the company has quietly moved into rather advanced DRAM DDR5 earlier this year, narrowing the gap with DRAM leaders.

Source: TechInsights

CXMT’s progress in HBM has been relatively slow. Prior to the surge in high-performance computing demand that began in late 2022, the company had not prioritized HBM technology, causing the company to fall behind the HBM development. Another reason, clearly, is the company's lagging development in DRAM, which underpins the front-end manufacturing for HBM.

Yet, CXMT is seeking to catch up with the HBM technology. In the second half of 2024, CXMT reportedly began mass production of HBM2. However, adoption of CXMT’s HBM is expected to remain at best, elusive, within China for now, given the availability of more advanced HBM products from SK Hynix and Samsung prior to restrictions, as well as the fact that local customers are unlikely to adopt the much less advanced products from CXMT. Moreover, CXMT has so far had only small volume production and shipment for its HBM products.

Currently, CXMT is working on HBM3 and planning for mass production in the following year. This should narrow the gap between CXMT and HBM leaders to about four years. Moreover, the firm aims to announce HBM3E and push for mass production in 2027; a quite ambitious roadmap given firm’s relatively immature DRAM and HBM technology.

Source: Ray Wang

Analysts attending this year’s SEMICON China, which took place in Shanghai, noted that they expect the rapid advancement in HBM through 2025, noting that HBM3E is the primary target specification for domestic HBM firms. While this does not indicate that China is on the verge of successfully developing HBM3E, the fact that domestic firms are actively developing around this specification implies meaningful progress in Chinese HBM technologies. At a minimum, it signals that China’s memory industry is working on the most cutting-edge HBM.

Looking through a more technical lens, CXMT appears increasingly capable of producing the DRAM die for both HBM2E and HBM3, building on its progress in DRAM. The company is currently able to manufacture DRAM at the 1y nm and 1z nm nodes used in these two generations of HBM. Another leading technology consultancy, TechInsights, confirmed in its January analysis that CXMT is capable of manufacturing DDR5 at the 1z nm The density of CXMT’s DDR5 is comparable to that of leading global competitors (Micron, Samsung, and SK Hynix) in 2021 though the chip exhibits a larger die size and an unverified yield rate.

CXMT’s R&D team is likely developing sub-15 nm DRAM nodes, specifically the 1α nm, which are essential DRAM nodes for HBM3E. Although CXMT will likely face major challenges in developing 1α nm without Extreme Ultraviolet Lithography (EUV), it is not impossible to develop 1α nm without EUV. In 2021, Micron debuted its 1α nm DRAM without the use of EUV, paving a potential track for CXMT to duplicate.

Source: Ray Wang

On the back-end process, for now, CXMT is likely to use TC-NCF bonding technology for its HBM product, given the company has similar access to most semiconductor manufacturing equipment (besides EUV) essential for HBM as other memory makers like Sasmsung and Micron prior to the December 2024 export controls. Even after the export controls, Hanmi Semiconductor continues to be the key supplier of TCB for various Chinese customers, which likely include CXMT, Tongfu Microelectronics, and other key players in China’s HBM space. Until very recently, Hanmi Semiconductor reportedly halted shipment of TC bonders to Chinese customers, likely due to the pressure from the U.S. government.

Taken together, CXMT’s capability in front-end and back-end technology in HBM will be key to watch regarding the future advancement for its HBM product, including HBM3E. In particular, the maturity of its front-end technology, namely D1z and D1a, will likely define the success of its forthcoming HBM product as its TC-NCF bonding should yet to be a problem to bite given firm’s stockpiled bonding equipment from South Korean equipment providers.

Given that CXMT has recently begun mass production of DDR5 using its 1z nm, yield issues with D1z are likely becoming less of a concern for its future HBM3 development although it will still take time for the firm to further improve yield and product quality. However, as the company aggressively pushes forward its front-end roadmap, it is expected to face significant challenges with the D1a node particularly in achieving competitive yield and scaling due to the absence of EUV lithography. As such, as of now, it is reasonable to believe CXMT is about 3 to 4 years behind leading memory makers in terms of HBM3 and HBM3E.

Source: Federal Register

In January 2025, BIS further tightened the definition of advanced node IC for DRAM to

• A memory cell area of less than 0.0026 µm²;

• A memory density greater than 0.20 gigabits per square millimeter; or

• More than 3000 through-silicon vias per die. (*Samsung’s HBM2 has > 5000 TSVs per die and SK Hynix’s HBM3 > 8000 TSVs per die)

The stricter rule could restrict CXMT’s ability to expand beyond 18nm as the October 2022 rule had allowed CXMT to pursue up to 1z nm despite the headline restriction at 18nm.

Looking ahead, besides paying attention to China’s front-end technology in HBM, it is important to closely monitor Chinese companies’ pursuit and potential adoption of hybrid bonding in their future HBM technologies. As previously emphasized, hybrid bonding could represent a pivotal turning point that reshapes the competitive landscape of the HBM industry. For the Chinese memory industry, hybrid bonding may offer a pathway to significantly accelerate their HBM development, perhaps not to surpass global leaders, but to more meaningfully narrow the gap.

Source: Knowmade

Clearly, Chinese companies are aware of hybrid bonding’s importance to HBM. Key HBM players such as CXMT and Tongfu Microelectronics have been investing in the research on hybrid bonding in recent years, with reports indicating a notable acceleration in their patent filings related to the technology since 2022 when China’s semiconductor industry faced increased U.S. restrictions.

Leadership in next-generation HBM will increasingly depend not only on a company's front-end DRAM manufacturing capabilities but also on its ability to be first to master and integrate hybrid bonding into its HBM products, setting itself apart from competitors. This should be the case for South Korean, U.S., and Chinese memory players.

Lei Jun, the founder CEO of Xiaomi, revealed on 16th May that Xiaomi is going to release its in-house SoC XRING O1. While some may be surprised by Xiaomi’s in-house silicon effort, this is in fact not their 1st SoC as Lei Jun alluded to in its Weibo post. Let’s take a look at the 10 years journey and explore the implication for merchant SoC giants such as Qualcomm & MediaTek.

Source: Weibo

Lei Jun on Xiaomi’s Chip Dream

很多朋友都很关心：做大芯片这么难，小米为什么还要做呢? 这个问题，在 11 年前，我们就反复问过自己，我在 2017 年发布会上也正式回答过。其实这次芯片重启，我们讨论了半年，原因非常简单：小米一直有颗“芯片梦”，如果想成为一家伟大的硬核科技公司，芯片是小米必须攀登的高峰，也是绕不过去的一场硬仗，在芯片这个战场上，我们别无选择!

Translated version

Many people are curious: making advanced chips is so difficult, why does Xiaomi still insist on doing it? This is a question we asked ourselves repeatedly 11 years ago, and I officially addressed it at our 2017 launch event. In fact, we discussed this chip reboot for half a year. The reason is very simple: Xiaomi has always had a "chip dream." If we want to become a truly great hardware tech company, chip is a summit we must climb. This is a tough and unavoidable battle. On this chip battlefield, we have no other choice.

Table of Content

1. Who is Xiaomi

2. History of Xiaomi’s In-House Silicon Efforts

3. XRING’s performance

4. How difficult is it to produce smartphone SoC?

5. How did Xiaomi overcome the BIS rule?

6. Implication for Qualcomm and MediaTek

7. Xiaomi’s Semiconductor Investment Portfolio

8. Conclusion

Who is Xiaomi?

Founded in 2010 by Lei Jun, Xiaomi has grown from a disruptive smartphone startup into one of China’s most influential tech giants. Lei Jun is a very famous entrepreneur and angel investor in China who became the CEO of Kingsoft in 1998 at the age of 29. He managed to turnaround the company before leading Kingsoft to IPO in 2007. In 2000, he founded Joyo.com as a side project while he was CEO of Kingsoft. Joyo.com was subsequently sold to Amazon for $75 million in 2004. His early investment in YY and UCWeb also paid off big.

Inspired by Steve Job, Lei Jun saw the potential of mobile internet as the next big wave and wanted to create a high quality made-in-China smartphone. Channel innovation was a key differentiation as it only sold its phones through ecommerce in the early days. By bypassing distributors and physical stores, Lei Jun was able to pass on cost savings to the end consumers. This strategy has led to Xiaomi’s reputation for quality at value pricing product and built a very loyal fanbase known as “Mi Fen”.

Source: Xiaomi

Xiaomi quickly became a global smartphone leader that has consistently ranked among the top five vendors globally. With a global smartphone shipment of 168.5 million in 2024, it is the 3rd largest smartphone OEM globally despite not having presence in the U.S. In 2021, Xiaomi took market share when Huawei was put on Entity List the year before. The loss of access to TSMC’s leading edge node and Android ecosystem put Huawei at a severe disadvantage. Since then, Xiaomi has continued to gain market share from peers such as Vivo and OPPO who were heavily reliant on physical stores distribution in the 2010s.

Source: Counterpoint

Beyond smartphones, Xiaomi has built an expansive AIoT (Artificial Intelligence of Things) ecosystem with over 900 million connected devices, including smart TVs, wearables, and home appliances. In 2024, the AIoT division generated a revenue of RMB104.1 billion, an increase of 30.0% YoY. The launch of an innovative top-flow air conditioner in 2024 led to sales growing more than 55%. This year, they have also launched a central air conditioner product that will take on Japanese giant Daikin.

Source: The Mail & Guardian

Source: Core77

In 2021, Xiaomi announced its intent to enter the EV (electric vehicle) market, which the market thought will be a drag on profits for many years. Xiaomi made headlines with the launch of its first EV sedan, the SU7, in March 2024. Within a year, Xiaomi SU7 deliveries is now higher than Tesla Model 3. The company will be launching a few more models over the years. As current capacity is unable to fulfil domestic demand, they will explore overseas market later on.

Source: Xiaomi

Source: CnEVPost

Xiaomi’s foray into EV completed its long-term vision of creating a "Human x Car x Home" smart ecosystem. With Xiaomi HyperOS as the foundation to connect smartphones, IoT and cars, it creates a seamless and intelligent experience for the users.

Source: Google Finance

Vertical integration kicks out the middleman, which allows Xiaomi to offer cheaper and better-quality product. In the IoT division, it has started to do in-house design of key categories and will be launching its smart home appliance factory at the end of 2025. Unlike BYD, vertical integration is not as extensive in Xiaomi despite its effort. This is due to China’s vast hardware supply chain and the low value-add to replace the suppliers. However, semiconductor design has the ability to create real product differentiation. In the smartphone division, the launch of SoC Xring is a culmination of more than 10 years of work.

History of Xiaomi’s In-House Silicon Efforts

Pinecone Electronics (2014 – 2017)

Xiaomi’s first serious foray into semiconductors started in 2014 with the establishment of Pinecone Electronics (松果电子), a subsidiary focused on designing application processors (APs). Initially, it licensed SDR1860 platform technology from another Chinese fabless company called Leadcore Technology. As Leadcore is part of Datang Telecom, it has numerous modem patents.

In February 2017, Xiaomi released its first in-house SoC, the Surge S1 (澎湃S1). This was fabricated on TSMC’s 28nm node and featured in the Mi 5C smartphone. Surge S1 was a 64-bit octa-core ARM-based SoC featuring 8 ARM Cortex-A53 cores.

While it lagged behind merchant silicon such as the Snapdragon 820 (Samsung 14nm) in performance, the launch made Xiaomi only the fourth smartphone brand globally to develop its own chips after Samsung, Apple, and Huawei.

Limitations in process technology and modem integration held the S1 back from mainstream adoption. Plan for Surge S2 was also shelved due to technical bottlenecks and cost pressures. S2 had multiple tape-out failures and the start of the 5G era further increased the technological barrier. In 2017, revenue scale was smaller as Xiaomi’s smartphone shipment was 96 million at 6% global smartphone market share.

Specialized Chips (2017 - 2024)

After setbacks in its SoC development, Xiaomi pivoted to specialized chips in narrower domains to steadily build its capabilities. This is more capital efficient while it continues to build its chip division capabilities.

In 2019, part of the Pinecone team was spun out to form Nanjing Big Fish Semiconductor (南京大鱼半导体有限公司) to focus on AI and IoT semiconductor. The rest of the Pinecone team continued to focus on smartphone chips.

Over the next few years, multiple specialized chips were released such as C1, P1, G1, and T1.

1. Imaging
   In 2021, Xiaomi launched the Surge C1, its first image signal processor (ISP), on a 28nm process. Surge C1 helped Xiaomi to achieve auto focus, auto exposure and accurate white-balance control in its algorithm. The dual-filter architecture improved image processing efficiency by processing both low-frequency and high-frequency signal at the same time. This was debuted in the foldable Mi MiX FOLD.

2. Fast Charging and Battery Management

   In 2021, Surge P1 was launched, and it enabled 120W single-cell fast charging with 97.5% power conversion efficiency. It is able to fully charge a 4600 mAh battery in 18 minutes. This was used in the Xiaomi 12 Pro.

   

   In 2022, Surge G1 was launched as a battery management chip that, together with the P1, formed the “Surge Battery Management System”. This improved overall battery health and safety. Xiaomi 12S Ultra was the first device to incorporate both G1 and P1.

3. Connectivity & Signal Enhancement
   In 2024, Xiaomi released the Surge T1 series to boost the reliability and quality of communication signal. This enables “dead-zone-free” coverage in devices like the Xiaomi 14 Ultra. An improvement of 24% in GPS performance, 37% in cellular communication performance and 16% in Wi-Fi Bluetooth performance are achieved.

   

Source: Hello Express

Return to SoC: XRING O1 (2025)

On 7th December 2021, Shanghai Xuanjie Technologies (上海玄戒技术) was established with a capital of RMB 1.5 billion. In 2023, capital injection was done to raise total capital to RMB 1.92 billion. The company is currently led by former Qualcomm senior director of product marketing Qin Muyun and former UNISOC CEO Ceng Xuezhong. It is Xuanjie that designed the new flagship SoC XRING O1.

Learning from their 2017 experience, Lei Jun knew that only by designing high-end flagship SoC can they control advanced semiconductor knowhow. When Xuanjie was established, an ambitious goal was set to produce flagship SoC at the most leading-edge node with performance and efficiency on par with Tier 1 global leaders.

Since inception, Xuanjie had spent a total of RMB 13.5 billion (USD 1.9 billion) in R&D expenses. Currently, the R&D team has more than 2500 people with an estimated R&D spend of more than RMB 6 billion in 2025. To give context, RMB 6 billion in R&D spending is more than what other listed Chinese semiconductor companies spent on R&D in 2024. There is no doubt that this is one of the biggest semiconductor design teams in China, one that has been hidden in plain sight.

Source: Listed companies annual report 2024

XRING’s Performance

XRING O1 (玄戒O1) is Xiaomi’s new flagship SoC that will debut in the Xiaomi 15S Pro smartphone, Pad 7 Ultra tablet and Watch 4s. The chip is built on TSMC’s N3E node with 19 billion transistors on an area of 109 mm². Comparing against Apple A18 Pro, XRING O1 has 5% lesser transistors count with 4% bigger die size. Considering this is Xuanjie’s 1st SoC, the specification is quite impressive.

Based on ARM V8 architecture, the XRING processor features a 10-core architecture, headlined by 2 ARM’s high-performance Cortex-X925 core clocked at 3.9GHz. Supporting it are 4 Cortex-A725 performance cores at 3.4GHz, 2 power-efficient Cortex-A725 cores at 1.9GHz and 2 power-efficient Cortex-A520 cores at 1.8 GHz. For daily use, only the 4 power-efficient cores will be utilized. The other 4 Cortex-A725 performance cores will be activated for gaming use, while the 2 big Cortex-X925 cores will be used for maximum performance.

In terms of benchmarking, XRING O1 achieved an ANTUTU score of 3,004,137 which is better than both Qualcomm’s Snapdragon 8 Elite and MediaTek’s Dimensity 9400. Both are the best merchant SoC chips you can find for smartphone in the market.

Source: Antutu

Source: Geekbench

There are a few reasons why XRING O1 is outperforming MediaTek and Qualcomm. The new chipset opts for an ambitious 10-core layout, a departure from the usual octa-core (8 cores) used by MediaTek and Qualcomm. It also includes two of ARM’s latest Cortex-X925 cores that clocked at a lofty 3.9 GHz for peak performance, whereas Dimensity 9400 only used 1 Cortex-X925 core.

In terms of power efficiency, XRING O1 loses out to A18 Pro slightly on the most intensive task.

In addition, it is paired with ARM’s Immortalis-G925 GPU with 16 cores that is 4 more than the 12-core Immortalis-G925 configuration in MediaTek’s Dimensity 9400. In the Aztec1440p and Manhattan 3.1 benchmark, XRING O1 outperformed A18 Pro by 43-57%. Power efficiency of the GPU is 35% better than that in A18 Pro. Compared to iPhone 16 Pro Max, the time taken to open an app is 30% faster for Xiaomi 15S Pro.

When playing mainstream MOBA game, Xiaomi 15S Pro is able to maintain a lower temperature than than iPhone 16 Pro Max. The difference is even more obvious during summer when the outdoor temperate is 35^oC.

Xiaomi also announced the 4th generation in-house ISP V4.

What is most surprising in the presentation is Xiaomi’s XRING T1 modem, which is their 1st 4G modem. Only a few companies globally (Qualcomm, MediaTek, Apple, Huawei, and Samsung) have successfully developed modem. Modem technology cannot be licensed from ARM and companies will have to buy from Qualcomm, MediaTek if they do not have in-house design capability. As much as Apple does not like Qualcomm, it took them many years before they successfully released C1 modem for iPhone 16e this year.

The 4G modem was hard work for Xiaomi which involved a team of more than 600 R&D engineers (60% of which have more than 10 years of experience). The modem was tested for 15 months across more than 100 cities and 150,000 km.

How difficult is it to produce smartphone SoC?

As written in the previous deep dive on MediaTek, SoC is a critical component for smartphone.

SoC is the brain of a smartphone as it integrates multiple components such as CPU for running the OS and processing, the GPU for rendering images and videos, memory controllers, modems for cellular connectivity, and other functions such as the ISP. By combining these elements into one compact chip, SoCs enable smartphones to be powerful and energy-efficient, handling everything from running apps to connecting to networks and processing multimedia content.

Building an in-house smartphone SoC is extremely difficult and resource intensive. It requires a combination of technical expertise, significant investment, licensing of critical IP from ARM and access to manufacturing infrastructure. It takes a few years from the initial design to logic design, physical design, verification and finally tape-out.

While licensing the IP cores from ARM can reduce the cost and time to market significantly, it is still not an easy task. The integration of AP, GPU, modem and multiple functions into a single SoC is done while ensuring it is optimized for performance, thermal and power efficiency. Xiaomi’s Xuanjie is rumored to have at least 1000 employees.

Source: notebookcheck, Dimensity 9400

Another major hurdle is the 5G modem. In the case of Xiaomi 15S Pro, they purchased the 5G T800 modem from MediaTek. Built on TSMC’s 4nm, T800 is designed for sub-6GHz and mmWave 5G networks. It can achieve download speeds of up to 7.9 Gbps and upload speeds of up to 4.2 Gbps.

To be competitive, the product has to be produced on leading edge 3nm and 5nm node at foundries such as TSMC. With increasing scrutiny from U.S. on China semiconductor efforts, this is becoming difficult as Chinese companies fall within the scope of Entity List. TSMC is also not allowed to manufacture 7nm and below AI chip for Chinese companies. Other than TSMC, access to EDA tools is also critical in the design of chips. In 2021, Xiaomi was considered by U.S. Department of Defense as a “CCMC” (Communist Chinese Military Companies) before it was subsequently removed.

Other firms that have attempted SoC development such as OPPO’s Zeku or LG’s Odin had exited due to cost and execution challenges. Zeku was established in 2019 before it was abruptly shut down in 2023. OPPO have been losing market share in the last few years and had shut Zeku due to the heavy ongoing investment requirement. This was a huge team of 3000 employees, and it was said that some was poached by Xiaomi after it was shut. Huawei had great success with HiSilicon before it was put on the entity list in 2020. Back then, HiSilicon’s 5G SoC was not losing out to top tier chips from Qualcomm.

Source: Counterpoint

This is why Xiaomi has adopted a more practical phased approach to its strategic priority of in-house silicon. It focused on ISP, PMIC and signal enhancer before it enters the SoC space again with external modem support. It reflects a recognition that success in in-house silicon requires not just ambition, but patience and long-term investment.

Another reason why Xiaomi is able to deliver XRING is that their revenue of US$ 56 billion is more than 3x bigger when Surge S1 was released in 2017. SoC development is an ongoing fixed cost that only large players such as Apple and Samsung can afford. The higher the market share, the cheaper the per chip cost is as it can be amortized over a larger volume. According to Lei Jun, each generation of chip costs US$ 1 billion in total cost. If used on 1 million smartphones, the cost per chip is as high as $1000 per phone. Strategic concern is obviously a more important consideration than profitability.

In-house SoC can provide significant competitive advantage through a tight integration of both software and hardware. Apple’s in-house SoC has been one of the most successful given its ability to control the iOS ecosystem. Apple is able to optimize iOS, macOS and app performance in ways that other OEMs cannot. This vertical integration also allows Apple to differentiate its products, accelerate innovation cycles and reduce reliance on external vendors like Qualcomm.

While Xiaomi does not have control over Android, it can still achieve a certain degree of software hardware optimization and better user experience. This is an important key pillar of Xiaomi’s strategy to go after the high-end smartphone market. In addition, it will also have better bargaining power over merchant silicon providers such as Qualcomm and MediaTek.

How did Xiaomi overcome the BIS rule?

There is a term in Chinese called 树大招风 (a tall tree attracts winds). Becoming higher profile runs the risk of an entry into U.S. entity list. Some also questions why Xiaomi is allowed to produce a sub-7nm chip if the BIS had banned 7nm chip.

Under the new rule by BIS in January 2025 on Implementation of Additional Due Diligence Measures for Advanced Computing Integrated Circuits, foundries and OSATs have to presume that any logic IC produced at 16/14nm node is designated ECCN 3A090.a and has to be subjected to a global licensed requirement.

To that end, this IFR imposes a broader license requirement for “front-end fabricators” and “OSAT” companies seeking to export, reexport, or transfer (in-country) certain “applicable advanced logic integrated circuits” under ECCN 3A090.a to or within any destination worldwide

In the absence of an attestation of the `total processing performance' and the `performance density' by an approved IC designer listed in supplement no. 6 to part 740 of the EAR, any logic IC produced using the “16/14 nanometer node” or below, or using a non-planar transistor architecture and destined for an item with an “aggregated approximated transistor count” exceeding the applicable number of transistors (as specified for the year of the export, reexport, or in-country transfer) within the package, or where the “aggregated approximated transistor count” of the final, packaged item cannot be confirmed by the “front-end fabricator” or “OSAT” company as described above, is presumed to be a 3A090.a item designed or marketed for a datacenter.

Source: BIS

The first way around it is to be an authorized IC designer, which is unlikely for Xiaomi.

Source: Wilson Sonsini

What Xiaomi did was through the 2nd mechanism where the IC chip is packaged by a front-end fabricator outside of China. Given the chipset is N3E, this is fabricated by TSMC in Taiwan. Next, the Xring O1 chip has a total of 19 billion transistors, which is below the 35 billion transistors threshold.

The second mechanism for overcoming the presumption relates to the location in which the IC die is packaged by the front-end fabricator. If that activity occurs outside Macau or a Country Group D:5 destination, then the presumption can be overcome if the front-end fabricator is able to attest to both of the following two facts:

• either "the 'aggregated approximated transistor count' of the final packaged IC is below 30 billion transistors" or "the final packaged IC does not contain high bandwidth memory (HBM);" and

• the "'aggregated approximated transistor count' of the final packaged IC" falls under certain thresholds.

The aggregated approximated transistor count thresholds are dependent on the year in which the export, reexport, or in-country transfer is completed. The threshold for 2027 is 35 billion transistors. For 2029 and later, the threshold is 40 billion transistors.

Source: Wilson Sonsini

Implication for Qualcomm and MediaTek

The impact of Xiaomi’s Xring is definitely negative to both Qualcomm and MediaTek, especially in the Chinese market. Both companies have benefitted a lot since the downfall of Huawei in 2020. Samsung’s foundry failure has also allowed Qualcomm to gain higher share within the high-end SoC market for Samsung. Now, the trend is slowly reversing with the comeback of Huawei and the release of XRING.

The trend in the last 5 years has been a shift towards merchant silicon as Huawei was put on entity list (banned from accessing TSMC’s technology in 2020) and Samsung was unable to deliver on its foundry process technology. For Galaxy S25, Samsung decided to use Qualcomm Snapdragon Elite 8 exclusively for the second time in recent years. While Oppo had tried to design their in-house chipset in 2019, they shut down the Zeku division in 2023.

However, the magnitude of the impact is manageable for now as Xiaomi will be launching XRing for a limited number of SKUs. The likely volume for XRing should be less than 5 million, which is only low single digit of its total smartphone shipment. The annual merchant silicon market between Qualcomm and MediaTek is more than 600 million units a year. Certainly, it is just a small dent.

Source: Counterpoint

Between Qualcomm and MediaTek, it is likely that Qualcomm will be impacted more. Xiaomi is known to be the biggest user of Qualcomm’s SoC in China, especially in the premium smartphone segment. Qualcomm's Snapdragon processors are predominantly featured in Xiaomi's flagship devices such as the Xiaomi 15 Ultra and Xiaomi 15.

Conversely, MediaTek's Dimensity series power many of Xiaomi's low to mid end models such as Redmi and POCO. For MediaTek, they will benefit as XRING likely uses external modem from MediaTek. The ASP of each modem should be north of $30.

As XRING can serve as a bargaining chip during price negotiations, this could lead to pricing pressure for both Dimensity and Snapdragon chips in the longer term. A shrinking merchant silicon market could also reignite a price war for market share between Qualcomm and MediaTek. While XRING is impressive, it is still far away from where HiSilicon was at the peak in 2020. The launch of 4G modem XRING T1 is not a good sign, although we won’t know when their in-house 5G modem is ready.

Xiaomi’s Semiconductor Investment Portfolio

Remember Lei Jun’s reputation as a Venture Capital (VC) investor in China? He had set up a very successful VC firm called Shunwei Capital in 2011.

Xiaomi has been actively involved in VC investing for many years too. It had raised a RMB 10 billion (US$ 1.4 billion) fund called Beijing Xiaomi Zhizao Equity Investment Fund (北京小米智造股权投资基金) in 2022 to invest in semiconductor related companies or in other areas such as smart manufacturing and new materials. The other main investment vehicle is Hubei Xiaomi Yangtze River Industry Investment Fund (湖北小米长江产业投资基金) which was established in 2017.

Source: Manjusaka

Through the two investment vehicles, Xiaomi had invested in more than 100 semiconductor companies in China. Some are well-known semiconductor companies in China such as Bestechnic, Black Sesame, BYD Semiconductor, Chipone, CXMT, GTA Semiconductor, Robosense, Smartsens and Vanchip. Xiaomi often comes in as the role of a strategic investor rather than a pure financial investor.

Conclusion

Beneath the surface, the company has quietly built one of China’s most ambitious in-house semiconductor design programs. From AP and ISP to connectivity chips and fast charging chips, Xiaomi’s multi-pronged silicon strategy is a critical element of its vertical integration push. It is also a potential catalyst for product differentiation as Xiaomi seeks to penetrate deeper into the high-end market.

A key lesson is that China’s most successful semiconductor efforts often come from successful system companies like BYD, Huawei and Xiaomi. For these firms, chip development is not an end in itself but a strategic step toward full-stack system innovation. It enables deeper hardware software integration and product differentiation. In fact, the most successful semiconductor startup of the past 20 years in the world has been Apple’s in-house silicon team. With control over the end product, these companies can tailor silicon to their specific needs to create a competitive advantage without the need to sell them externally.

For both Qualcomm and MediaTek, the short-term impact is limited for now. Investors should not panic as both companies are pursuing their new growth drivers beyond smartphone. For fabless companies, the biggest threat has always been the system companies (Apple, Google, Amazon, Meta, Samsung, BYD, Xiaomi).

MediaTek, headquartered in Hsinchu, Taiwan, is a leading fabless semiconductor company specializing in the design of smartphone system-on-chip (SoC). MediaTek has grown to become the world's fifth largest fabless semiconductor company, powering over 2 billion devices annually.

The company's product portfolio encompasses a wide range of applications, including mobile devices, home entertainment systems, connectivity solutions, and Internet of Things (IoT) products. MediaTek's SoCs are integral to smartphones, tablets, smart TVs, routers, and various smart home devices. Notably, its Dimensity series has positioned MediaTek as a significant player in the 5G smartphone chipset market, offering high-performance solutions at competitive price points.​ The company is embarking on its next growth phase as it expands its TAM through PC, automotive and AI ASIC.

Table of Content

1. Founder Tsai Ming-Kai - Godfather of Chip Design

2. History of MediaTek

3. Revenue Overview

   1. Mobile Phone

   2. Smart Edge (Wi-Fi, automotive, AI ASIC, PC)

   3. PMIC

4. Disciplined Capital Allocation

5. Financials

6. Risks

7. Conclusion

   ---

Founder Tsai Ming-Kai - Godfather of Chip Design

The history of MediaTek cannot be separated from its founder Tsai Ming-Kai, who is also known as the Godfather of Chip Design in Taiwan. Born in 1950 in Taiwan, Tsai Ming-Kai graduated from National Taiwan University with a degree in electrical engineering, later earning a master's degree from the University of Cincinnati in Ohio.

Source: Forbes

Tsai began his career at the Industrial Technology Research Institute (ITRI), where he led the microcomputer IC design department. ITRI, a government backed research institute established under then Minister of Economic Affairs Sun Yun-suan, played a pivotal role in Taiwan’s industrial development and was instrumental in the creation of spin-offs such as TSMC.

In 1976, ITRI signed a technology transfer license agreement for CMOS technology with Radio Corporate of America (RCA). ITRI sent a group of engineers to RCA for training in semiconductor. This group of engineers included Robert Tsao, founder of UMC; Tsai Ming-kai, founder of MediaTek and F.C. Tseng, a key lieutenant when TSMC was founded.

Subsequently, Tsai joined UMC in 1983 to form the IC design group as UMC wanted to increase their fab utilization rate through internal IC products. He was promoted to President of UMC’s product business units, where he directed the company’s efforts in storage, CPU, consumer electronics, and multimedia chip development. Tsai’s 15 years at UMC allowed him to grow from an engineer into a businessman.

A decision was made by UMC to transform into a pure-play foundry in 1995, which led to the spin-off of multiple design subsidiaries such as Novatek, AMIC, ITE Tech, Davidcom, Faraday and MediaTek. Both MediaTek and Novatek are among the world’s top 10 biggest fabless companies. Tsai chaired and managed many of these design houses that were spun out of UMC.

Tsai has a strong interest in strategy, often drawing inspiration from Michael Porter and Andy Grove. His keen strategic sense has been a key factor behind Mediatek’s success as Asia biggest fabless company.

One key insight is that fabless design has a lower barrier of entry

IC design doesn’t need to be cutting-edge; meeting market needs is what defines a successful design

History of MediaTek - Transformation and Adaptation

Spun out in 1997, MediaTek was known as the most promising design subsidiary of UMC. MediaTek's decoder ICs for CD-ROM and DVD-ROM had high barriers to entry and captured over 80% of Taiwan’s CD-ROM market.

Former Chairman of TSMC Mark Liu said “Tsai Ming-Kai, the founder of MediaTek, has been able to re-invent MediaTek time and again with new business models to turn challenges into opportunities in the unpredictable and fast-moving technology industry.”

Entry into mobile phone market - A tumultuous journey for 3G and 4G

In 2000, MediaTek evaluated the mobile phone chip industry and felt it would be a critical growth area for the company. A major investment was made and MediaTek started to produce chipset for 2G feature phones in 2004. Tsai pioneered a turnkey solution that bundled hardware and software for feature phone chipsets, which dramatically lowered entry barriers for handset manufacturing. His strategic insight was to remove friction for system makers and own the ecosystem. This strategy enabled a wave of low-cost “Shanzhai” (white-box) phones in China, making MediaTek the dominant supplier of feature phone SoC during that era​.

The next evolution came when the mobile market shifted from 2G feature phones to 3G smartphones. This period was challenging as Qualcomm’s lead in 3G (as the inventor of CDMA technology) meant MediaTek lagged initially​. MediaTek spent a few years catching up before securing 45% market share (+29% YoY) in China smartphone market in 2012.

A similar issue happened again in 2014 with China’s adoption of LTE. Back in 2009, Taiwan’s government was backing the WiMAX standard for 4G, but the global market ultimately coalesced around LTE. MediaTek, initially aligned with WiMAX, found itself two to three years behind when it pivoted to LTE, delaying its chip rollout and leading to more than 20% market share loss between 2015 and 2017. Another strategic misstep was to go after the high-end segment when MediaTek is known to only have cost competitiveness in the later part of the cycle.

Source: MediaTek

ex-TSMC CEO Rick Tsai was hired in 2017

Tsai Ming-Kai later acknowledged the strategic misstep and made the decisive call to wind down the 4G project ahead of schedule, swiftly reallocating resources toward 5G R&D. Determined to avoid falling behind again, MediaTek set its sights on becoming a technological and commercial leader in the next generation of wireless.

At the same time, Tsai Ming-Kai hired ex-TSMC CEO Rick Tsai to become the new CEO of MediaTek. For those who are not familiar with the history of TSMC, Rick Tsai was the initial successor of Morris Chang in 2005 before Morris Chang came back to reclaim the CEO role in 2009. Contrary to public perception, Rick Tsai was still Morris Chang’s most preferred successor after the layoff saga.

Source: Computex

Tsai Ming-Kai acknowledged that MediaTek has grown too big and enlisted Rick Tsai in 2017 to impose operational discipline on the company. Rick Tsai also recognized the need to bet big on 5G early so that it does not lose out to Qualcomm early in the cycle transition.

When 5G adoption came in 2020, MediaTek was able to release the Dimensity series, a cost-competitive 5G SoC, that was earlier than Qualcomm. This is the 1st time since the botched 3G and 4G transition that MediaTek is neck-to-neck in competition with Qualcomm. The success of the 5G transition can be seen from MediaTek’s share price which appreciated more than 500% from 2019 to 2021.

Source: Google Finance

With 5G adoption maturing and the smartphone market reaching saturation, MediaTek has begun seeking new growth drivers. In the coming years, the company is poised to expand into new markets and applications, marking the next phase of its growth journey. We will explore these new initiatives later in the deep dive.

Revenue Overview

3 main product groups of MediaTek

1. Mobile phone SoC is the core business of MediaTek, accounting for 60% of its total revenue

2. Smart Edge is a diversified portfolio of chips for the edge such as wireless connectivity (Wi-Fi, Bluetooth), Digital TV and Set Top box, Edge AI, IoT and ASIC design solution

3. Power IC focuses on power management IC (PMIC), most of which came from the acquisition of Richtek in 2015

1) Mobile Phone

MediaTek’s Helio and Dimensity (5G) SoC power smartphones across tiers, especially Android devices. MediaTek is the leading supplier of smartphone SoC by unit volumes thanks to its strength in mid-range and value smartphones. Many feature phones today are also still powered by MediaTek.

SoC is the brain of a smartphone as it integrates multiple components such as CPU for running the OS and processing, the GPU for rendering images and videos, memory controllers, modems for cellular connectivity, and other functions such as the ISP. By combining these elements into one compact chip, SoCs enable smartphones to be powerful and energy-efficient, handling everything from running apps to connecting to networks and processing multimedia content.

Source: Fonearena, Dimensity 9200

Processor technology is largely licensed from ARM Holdings and MediaTek is required to pay a royalty fee to ARM for every smartphone SoC they sold. ARM dominates the smartphone SoC market, with its architecture powering over 99% of mobile devices globally. This dominance stems from ARM's energy efficient designs, which are crucial for battery-powered devices like smartphones. The widespread adoption of ARM's architecture ensures broad compatibility across applications and operating systems, facilitating a seamless user experience and simplifying development for software engineers. On the other hand, the x86 architecture dominates the PC and server CPU market.

In the past, Qualcomm used to have an internal R&D team that was licensed to improve the ARM architecture. However, this is less important these days given that ARM has gotten really good at it.

​The key differentiation for smartphone SoC lies in the die size and the modem technology for cellular connectivity. Die size determines the cost structure and the power consumption of the smartphone SoC. Higher power consumption is frowned upon due to the limited battery life of a smartphone. Modem or the baseband processor plays a crucial role in ensuring effective and efficient communication over wireless networks by processing baseband signals, which are the raw signals ready for transmission or received after being converted.

For MediaTek’s Dimensity 9400 SoC which is built on ARM V9.2 architecture, MediaTek licensed Cortex CPU and Immortalis GPU IP from ARM. NPU 890, ISP Imagiq 1090, Display MiraVision 1090 and the modem technology are designed by MediaTek. NPU is neural processing unit which allows smartphones to handle AI inferencing requirement.

Source: notebookcheck, Dimensity 9400

Overview of the smartphone SoC market

Global smartphone unit shipment peaked at 1.5 billion units in 2016 and has been on a slow decline since. Global smartphone unit shipment was 1.2 billion units in 2024 and is likely to remain at similar level given high smartphone penetration rate and a slower replacement cycle. Smartphone growth is available only in certain regions such as Africa and India where smartphone penetration rate remains at below 50%. Replacement cycle is getting longer due to the lack of significant new innovation for smartphone.

Source: S&P Global

The smartphone SoC market can be split into 2 segments: merchant silicon and in-house custom silicon. Merchant silicon vendors, such as Qualcomm and MediaTek, supply SoCs to a broad range of smartphone OEMs like Xiaomi, Oppo, Vivo, and Samsung. Conversely, in-house custom silicon is developed by companies like Apple, which designs its own A-series chips for iPhones exclusively, and Samsung, which produces Exynos chips for select models. In-house custom silicon makes a lot of sense for Apple given its control of the iOS ecosystem and ability to optimize the iPhone. While Apple is still using Qualcomm’s modem for its iPhone SoC, this is set to change as iPhone 16e has started to use Apple’s in-house modem C1.

The trend in the last 5 years has been a shift towards merchant silicon as Huawei was put on entity list (banned from accessing TSMC’s technology in 2020) and Samsung was unable to deliver on its foundry process technology. For Galaxy S25, Samsung decided to use Qualcomm Snapdragon Elite 8 exclusively for the second time in recent years. While Oppo had tried to design their in-house chipset in 2019, they shut down the Zeku division in 2023.

Source: Counterpoint

Source: IDC, MS

For the merchant silicon market, it is largely dominated by Qualcomm, MediaTek and UNISOC from China. The turning point for MediaTek was in 2020 when 5G first took off in volume. As explained earlier, MediaTek was early to invest in 5G technology and it’s 5G chipset was no longer inferior to Qualcomm. In addition, MediaTek was in a better position during the period of chip shortage in 2021 due to a better relationship with TSMC. Back then, Qualcomm was trying to dual source between TSMC and Samsung which did not end up well for Qualcomm.

Post the 5G cycle, MediaTek’s volume share is relatively stable and it started to target the premium market with Dimensity 9000 series. It is not easy to target the premium market in China as consumers often have the impression that Snapdragon-powered phone is better than MediaTek’s. With an improved chipset and the OEMs facing cost pressure in a stagnant smartphone market, MediaTek’s Dimensity 9000 series was able to achieve $1 billion in revenue in 2023 and $2 billion in revenue in 2024. Powered by TSMC’s 3nm technology and Arm V9 architecture, MediaTek’s Dimensity 9400 is almost on par in performance with Qualcomm’s Snapdragon 8 Elite. The ASP of Dimensity 9400 is more than $100, which is several times more than the average 5G chipset.

Source: Antutu

Source: Counterpoint

Moving forward, smartphone SoC is a stable cash cow for MediaTek given stagnant smartphone market growth and limited market share gain opportunity. MediaTek will have to wait for AI smartphone or 6G to take off before its smartphone SoC revenue can resume its growth momentum.

2) Smart Edge

MediaTek has a wide range of product portfolios for the smart edge. We will first look at the more mature segments before moving to the new growth initiatives.

Digital Television and Display SoCs

MediaTek is the world’s leading supplier of chips for smart TVs, digital TVs, and set-top boxes. The MStar merger in 2012 made MediaTek dominant in this segment. Its SoCs service smart TV (for brands like Sony, Sharp, Xiaomi, etc.), handling tasks from video decoding and upscaling to app execution. These chips often integrate display controllers, audio processors, and connectivity. MediaTek’s TV chip business is a stable cash cow given the mature TV markets.

Connectivity: Wi-Fi & Bluetooth

MediaTek is a major player in connectivity chips. The 2011 acquisition of Ralink gave it a strong foothold in Wi-Fi routers and combo chips for devices. Today, MediaTek’s Filogic line covers Wi-Fi 6/6E and Wi-Fi 7 solutions for routers, broadband gateways, and IoT devices. It also produces Bluetooth and GNSS (GPS) chips often used alongside its smartphone SoCs or in standalone applications (e.g. wireless earbuds, wearables). This business benefits from the global demand for wireless connectivity in smartphones, PCs, smart home gadgets and industrial IoT. Boosted by the transition to Wi-Fi 7, MediaTek expects its Wi-Fi revenue to double this year as the ASP of Wi-Fi 7 SoC is more than double of Wi-Fi 6/6E.

Source: Lite-point

New Growth Drivers: PC CPU, Automotive, ASIC

ARM-based PC CPU

MediaTek has significantly expanded its presence in the Chromebook market through its Kompanio series processors. The Kompanio 500 series, including the Kompanio 520, powers affordable Chromebooks like the Lenovo 100e Gen 4 and ASUS CM14. MediaTek’s Kompanio Ultra 910, marks a significant leap in Chromebook capabilities. Built on a 3nm process, it features an all-big-core CPU architecture, an 11-core GPU with ray tracing support, and an 8th-generation NPU delivering up to 50 TOPS of AI performance.

According to the Market Data Forecast, the Chromebook market is expected to grow at 3.5% CAGR from 2025 to 2033. This is propelled by increasing demand for affordable, cloud-centric computing solutions across education, enterprise, and personal use sectors. MediaTek is currently the No 1 ARM-based Chromebook CPU provider and will continue to take share from Intel, which is the leading x86 CPU provider for the Chromebook market.

Source: MediaTek

In middle of 2024, Qualcomm officially released Snapdragon X Elite chip for Windows on ARM (WoA) PCs. Given that Qualcomm’s exclusivity agreement with Microsoft had ended late last year, MediaTek is expected to announce its ARM-based CPU over the next few months. This ARM-based CPU is designed in collaboration with NVIDIA and MediaTek is expected to receive royalty fee from it.

ARM-based PCs offer notable advantages, particularly in power efficiency and thermal management, making them ideal for notebook and extended battery life scenarios. These attributes have led to their widespread adoption in mobile devices and are increasingly influencing the laptop market. However, ARM-based PCs still face challenges, notably in software compatibility, as many applications are optimized for x86 architectures. With increasing competition from ARM-based vendors such as Qualcomm, MediaTek and Apple, this is a structural headwind for Intel in an increasingly crowded market.

In January 2025, NVIDIA released GB10 Grace Blackwell Superchip for NVIDIA Project DIGITS in collaboration with MediaTek. This is a personal AI supercomputer designed for the public to gain access to high performance AI computing. Although the GB10 is priced at $3000, the revenue contribution will be limited for MediaTek as the main GPU and CPU designs come from NVIDIA.

While PC CPU is a new market for MediaTek, it will not be a significant driver of the long-term value of the company. The PC CPU TAM is $30 billion and profitability may not be high in a crowded market. Assuming MediaTek can capture 10% of the CPU market in the long-term, revenue contribution is $1.5 billion at best as there is revenue sharing with NVIDIA. This will represent 10% of MediaTek’s revenue in 2024.

Automotive

MediaTek launched its Dimensity Auto platform in April 2023 to enter the infotainment SOCs market. This platform aims to provide infotainment SoCs, telematics, connectivity solutions and eventually ADAS chips for vehicles.

Qualcomm had a head-start here with a $45  billion design-win pipeline as of 2024, but MediaTek is leveraging partnership with NVIDIA to catch up. As Qualcomm pushes deeper into the autonomous driving space with the Ride Platform, the partnership between NVIDIA and MediaTek is highly complementary and strategically beneficial for both. NVIDIA leads in autonomous driving with its powerful ORIN GPU platform, while MediaTek brings strength in modems and infotainment which are key capabilities required to secure cockpit design wins. The partnership is necessary to go up against Qualcomm which is getting more embedded within the automotive semiconductor market.

Source: Qualcomm Investor Day 2024

At the recent Automobile Shanghai show, MediaTek has unveiled its flagship Dimensity Auto Cockpit Platform (C-X1) marking a significant milestone in its collaboration with NVIDIA. This C-X1 SoC is fabricated on TSMC's N3 process and integrates an NVIDIA Blackwell GPU, bringing advanced ray tracing and AI capabilities to the automotive cockpit. It also supports 5G technology, complying with 3GPP Release-17 and Release-18 standards.

Source: MediaTek

In Q2 2023, the company reported over $1 billion in automotive design wins with revenue starting to ramp in 2026​. This has the potential to be a much bigger market than both PC CPU and smartphone SoC market. In Qualcomm Investor Day 2022, they had estimated a TAM of $100 billion for the automotive market by 2030 based on connectivity, cockpits and autonomous driving solutions. While EV adoption might have hit a bump, there is no question that cars continue to get smarter.

Source: Qualcomm Automotive Investor Day 2022

If MediaTek is able to capture 10% of the automotive infotainment and connectivity market, this will be $4 billion in incremental revenue or 25% of its 2024 sales. While the automotive push takes time to realize revenue due to the longer qualification cycle, it is stickier as carmakers tend to use a chip platform for many years.

AI ASIC

Hyperscalers like Google, Amazon, and Meta are increasingly developing their Application-Specific Integrated Circuit (ASIC) for AI acceleration, networking, and specialized workloads. Broadcom had estimated an AI SAM of $60- 90 billion from its 3 customers by 2027. There are a few reasons why investment in ASIC will continue

1. FAMG have the scale to invest in their custom silicon

2. They can lower cost of ownership in cost-sensitive AI applications by paying lower than 70% gross margin to design service provider

3. Custom silicon acts as a negotiation tool against the dominance of NVIDIA in the GPU space. They are also useful when NVIDIA’s GPU delivery schedule is delayed

4. For internal workloads, hyperscalers are able to optimize both the software and hardware through the control of their in-house ASIC

MediaTek, with its broad silicon design expertise, sees an opportunity to serve as a design and manufacturing partner for these ASICs projects. They had past experience working on both consumer and enterprise ASIC projects with customer such as Cisco and game consoles provider.

The company is working with Google to develop the next generation of its Tensor Processing Unit (TPU) AI chips​. Google has traditionally worked with Broadcom on TPU, but is turning to MediaTek for cost advantage and supply chain diversification effort. With its strength in Serializer/Deserializer (SerDes), Broadcom is known to charge a gross margin as high 70% for the TPU project.

MediaTek expects to recognize revenue from the N3 TPU 7e project starting from 2026. Revenue contribution is expected to be a few billions given that Google is estimated to have spent $6 to 9 billion on TPU 5 in 2024. MediaTek is also likely to be featured in the next-generation N2 TPU 8e project.

The main advantages of MediaTek in the ASIC market lie in its SerDes capabilities and close relationship with TSMC. SerDes (Serializer-Deserializer) IP is an analog IP that is a cornerstone for next-generation ASIC designs as it enables ultra-high speed data transfer. SerDes converts parallel data into serial data (a single high-speed data stream) for transmission, and converts it back to parallel data at the receiving end.

To support 1.6T networking, AI accelerators will require 224G SerDes (224 gigabits per second) over 8 lanes. While lower speed SerDes may be used, this will increase the number of lanes and hence power consumption. Broadcom, MediaTek and Synopsys are known to have credible 224G SerDes IP. For Broadcom, its strength in SerDes is the main reason why Google has to pay a very high gross margin for the TPU project. According to Irrational Analysis, MediaTek’s 224G SerDes has improved significantly. Having in-house SerDes also leads to cost saving as design service provider does not have to pay license fee to 3rd party IP vendors such as Synopsys or Cadence.

Source: IPnest

Another advantage of MediaTek in this market is its close relationship with TSMC. As one of the biggest customers of TSMC, MediaTek receive better pricing and wafer capacity allocation.

Lastly, it was also announced at GTC 2025 that MediaTek will integrate NVIDIA’s NVLink IP into its ASIC design service. This is yet another sign of a very close partnership between MediaTek and NVIDIA.

In November 2024, MediaTek took a stake in Taiwan design service provider Alchip. This could pave the way for future partnership where MediaTek can work on the front-end part of the design before passing the back-end chip design to Alchip.

One caveat for this business is that gross margin is lower than MediaTek’s corporate average of 48%. At the operating margin level, the margin dilution is not as high as bulk of the engineering expenses have occurred at the NRE stage. Another issue is that ASIC projects are known to face delay due to rising complexity or lack sufficient performance level to achieve mass production. For MediaTek, the TPU project was expected to contribute revenue in 2025 but has since been pushed back to late-2026. In addition, MediaTek is also in the running for some involvement in the next-generation Maia project by Microsoft.

Source: SemiEngineering

3) PMIC

In 2015, MediaTek acquired Richtek Technology, Taiwan’s leading analog IC company. Richtek initially focused on motherboard PMICs, but over time shifted its end applications toward mobile devices as the market evolved. Main product is power management chips that regulate voltages and battery charging in smartphones and laptops. These PMICs are often bundled with its SoCs (in reference designs for phone makers) and sold to 3rd parties. This vertical integration helps optimize device power consumption and gives MediaTek a larger share of the silicon content in devices.

Disciplined Capital Allocation and Capital Return

MediaTek has built a strong track record of generating attractive returns on its investments. Both MStar Semiconductor and Richtek Technology have become integral parts of MediaTek’s core business. Notably, MediaTek successfully doubled Richtek’s sales within five years of completing its acquisition, demonstrating effective integration and growth execution.

In 2011, MediaTek invested approximately US$20 million for a 20% stake in Goodix Technology, a Chinese company specializing in fingerprint sensors. Upon exiting the bulk of its investment in Goodix, MediaTek realized an impressive investment gain exceeding US$1 billion.

Similarly, in May 2016, MediaTek sold AutoChips to Chinese digital map provider NavInfo for US$600 million. This marked a more than 100% return on its investment, just three years after initially investing in AutoChips in 2013. These successes highlight MediaTek’s disciplined approach to capital allocation and its ability to unlock value across different segments of the semiconductor ecosystem.

Currently, MediaTek still have 3 publicly listed companies as their golden goose.

1. 66.4% stake in Airoha Technology (6526 TT)

   Airoha is a market leader in Bluetooth and Global Navigation Satellite System (GNSS) chipset. It is also in the midst of sampling 100Gbps PAM4 DSP in 2025.

   MediaTek first invested in Airoha in 2007 before MediaTek bought out the remaining 75% stake for NT$5 billion (US$166 million) in 2017. Their stake in Airoha is currently worth NT$57.4 billion (US$1.78 billion), a return of more than 10x in 8 years.

2. 28.8% stake in SigmaStar (301536 CH)
   SigmaStar is a leading provider of video surveillance chip in China. This is a spin-off from Mstar which they acquired in 2012.
   
   Their stake in SigmaStar is worth RMB6.7 billion (US$920 million).

3. 23.55% stake in Vanchip (688153 CH)
   Vanchip is a leading domestic suppliers of power amplifiers in China.

   
   Their stake in Vanchip is worth RMB3.1 billion (US$424 million). MediaTek first acquired the 40% stake in Vanchip for US$40 million in 2019. Another 10-bagger winner for MediaTek in just 5 years.

As a fabless semiconductor company, MediaTek operates with an asset-light model that generates strong free cash flow, enabling consistent shareholder returns. Reflecting this financial strength, MediaTek has maintained a generous dividend policy. In 2021, the company increased its dividend payout ratio to 80–85% of earnings, reinforcing its commitment to returning capital to shareholders.

Alongside this, MediaTek announced a special dividend of NT$100 billion (equivalent to NT$15 per share), distributed over the period from 2021 to 2024. This special dividend was funded from excess cash balance, showcasing the company’s robust balance sheet and confidence in its long-term cash generation.

Financials

As mentioned earlier, the 5G cycle was a big success for MediaTek. Their revenue more than doubled from 2019 to 2022 and net income grew by 500% in that period. In 2022 and 2023, inventory correction and charges took a hit on their bottom line during the semiconductor downcycle. Moving forward, consensus estimates expect MediaTek to grow its earnings by close to 50% from 2024 to 2027.

MediaTek has also proven its ability to maintain its margin at a high level 5 years after the initial 5G adoption. Given that Qualcomm does not have a cost advantage over MediaTek, we do not expect a price war. The company generates plenty of free cash flow each year and pays a big portion of it as dividend.

Risks

1. Xiaomi’s In-House Custom Silicon Development
Following the footsteps of Apple and Samsung, Xiaomi has signaled intentions to internalize key component like smartphone SoC to better differentiate its products. This is likely to have a bigger impact on Qualcomm. Rumor is that the in-house 4nm SoC “Xuanjie” or “XRing” will be released in 2025 although it is a generation or two behind the merchant silicon. Xiaomi is likely to rely on external modem provider for this SoC. This trend toward vertical integration among top smartphone OEMs could pressure MediaTek’s unit volumes over time.

2. Lag Between New Growth Drivers and Revenue Contribution
MediaTek’s diversification into automotive (Dimensity Auto), PC (Windows on Arm CPUs), and custom ASICs (hyperscaler partnerships) offers promising long-term growth, but these segments have long design cycles and gradual ramp-ups.

Automotive chips, for example, require stringent qualification processes and can take 3–5 years from design win to meaningful revenue contribution. Similarly, cloud ASICs is still in early stage and may not scale materially until 2026 or later. While MediaTek’s smartphone business is maturing, new drivers may take time to offset the cyclicality and slower growth in the core mobile segment, potentially leading to near-term growth volatility.

3. China Smartphone Subsidy
The Chinese government’s subsidy has created pull forward demand for consumer electronics such as smartphone. Historically, subsidies to stimulate domestic demand have led to demand distortions and inventory volatility in the supply chain. MediaTek is vulnerable to inventory correction once subsidies fade given their heavy exposure to Chinese OEMs.

Source: Counterpoint Research

Conclusion

MediaTek’s journey from a CD-ROM chipset maker to Asia’s largest fabless semiconductor company is a testament to its adaptability and strategic foresight. Under the leadership of Tsai Ming-Kai and Rick Tsai, the company has consistently navigated market transitions. It has captured leadership in smartphone SoCs and expanded into adjacent markets like connectivity and PMIC.

As 5G matures and smartphone growth plateaus, MediaTek is positioning itself for its next chapter by targeting automotive, AI ASICs, and ARM-based CPUs. While these new initiatives present long-term growth opportunities, they come with extended design cycles and execution risks. Nonetheless, MediaTek’s strong balance sheet, disciplined capital allocation, and track record of reinvention underscore its potential to remain a pivotal player in the evolving semiconductor landscape.

Disclaimer - The article is for informational and educational purposes only and should not be considered investment advice. While every effort is made to ensure the accuracy and reliability of the information presented, there is no guarantee to its completeness or accuracy.

The views expressed are solely those of the author and may be subject to change without notice. Discussion is based on publicly available information and reflect the author's independent analysis and judgment at the time of writing.

Tan Lip-Bu Sets the Tone

In his inaugural keynote as Intel's CEO, Tan Lip-Bu emphasized a customer-centric approach, urging partners to provide candid feedback to drive continuous improvement. Tan's message was clear that Intel is fully committed to its foundry business and is taking decisive steps to earn the trust of its customers.

More important today is to listen to our customer. I would love your feedback so that we can better serve you.

Now I've been the CEO for about 5 weeks now. And then some of the people are asking me, since I joined Intel, Lip-Bu, "are you committed to the foundry?" The answer is yes. I'm so excited today to share with you. I'm committed to make the Intel Foundry successful, and I know there are areas we need to improve. I'm determined to strengthen our road map and our partnership and our execution going forward. As we drive this improvement, we see a lot of opportunity ahead of us.

For once, we might have an Intel CEO who truly understands what it takes to succeed in the foundry business.

I really embrace the industry standard IP and EDA so that we can really help you and serve you better. And this is truly a service business, and that is built on the foundational principle of trust. And you have to be patient to earn your trust. And then we have to really driving some of the technology to make sure that the yield and performance and reliability meet your requirement.

We will be guided by the Voice of the Customer, all of you, and we'll act on your feedback. We are humble in that approach, as you can tell, because we know your success is matter the most than anything else. And we work every day to earn your trust.

Source: Intel

TSMC has always emphasized trust as a core value of the company given that trust is the bedrock of the foundry business. Unlike IDMs, foundries don’t sell end products. They sell reliability, confidentiality and execution. When companies like Apple and NVIDIA hand over their most sensitive chip designs to a foundry, they require assurance that TSMC would never compete with them and to deliver as promised. Integrity and trust go hand in hand.

Source: TSMC

Seeing Intel labels trust as a foundational principle is both refreshing and assuring. Trust is not about exaggerating your future technology roadmap potential, but to provide a reliable roadmap that customers can depend on to deliver their new products on time. Of course, Intel’s challenge is unique as it’s both a foundry and an IDM competitor. Whether customers believe Intel can replicate the trust TSMC earned over 30 years will be central to its foundry ambitions. Tan Lip-Bu also understands that foundry is a service business. The mindset change is important as foundry is much more than having superior technology.

In another sign of Tan Lip-Bu strong interpersonal relationship, CEOs of all 3 major EDA tools Sassine Ghazi (Synopsys), Anirudh Devgan (Cadence) and Mike Ellow (Siemens EDA) went on stage.

Intel shared that they had invested a total of $90 billion on property, plant, equipment and R&D. For comparison, TSMC had spent a total of $150 billion in the same period which is more than 50% higher than Intel. This year, Intel will spend a gross capex of $18 billion (net capex of $8 to $11 billion) while TSMC will spend a total capex of $38 to 42 billion. Leverage, lack of scale, low utilization rate and a core business under threat remain impediment as Intel embarks on this capital-intensive business. TSMC is expected to grow its revenue by more than 25% to $110 billion this year, while Intel’s revenue is expected to decline by mid-single digit to $50 billion.

Source: Intel

Intel Foundry Process Roadmap

The main highlight of the process roadmap is 18A, 18A-P, 14A and 14A-E

Source: Intel

Intel 18A Is Ramping

Intel’s 18A will be the 1^st node to feature two key technology innovations in RibbonFET, Intel’s gate-all-around transistor architecture, and PowerVia, their take on backside power delivery. 18A will boast a density improvement of 30%, performance/watt improvement of 15% relative to Intel 3.

Back in 2021, Pat Gelsinger came out with the target to achieve 5 nodes in 4 years. Intel is on track to meet the goal as 18A is in risk production with volume ramp expected later this year. However, real volume ramp of Panther Lake (built on 18A) will be in 2026.

Defect density continues to improve in Q4 2024 and Q1 2025. Intel had previously revealed that their D0 (defect density) is 0.4 for 18A in September 2024. Intel’s D0 is likely to be somewhere between 0.2 to 0.3 right now. While this is higher than TSMC’s D0 of <0.2 for N2, Intel is on track for mass production of 18A.

Source: TSMC Technology Symposium 2025

Introduced during the event, Intel 18A-P is a newly announced enhancement of Intel’s 18A process node. Intel’s 18A-P is a performance-enhanced variant of 18A optimized for customers demanding better performance.

With mass production in 2026, 18A-P has design rule compatibility with 18A and offers an 8% improvement in performance. Because of the design rule compatibility, most of the IP will be able to port over from 18A to 18A-P seamlessly. Again, this is like what TSMC has always done in introducing application specific derivatives nodes that are more suitable for clients. Design rule is usually compatible between derivatives nodes. N3E was introduced at a lower cost to replace N3B and now TSMC offers N3X, N3A and N3C.

With the better performance and more mature IP, 18A-P will become more competitive in the foundry market.

Source: TSMC Technology Symposium 2025

Another variant, 18A-PT, has also been introduced with the main feature being the addition of TSV. This will be more suitable for AI applications where 18A-PT can be used as a base die for further integration with HBM.

Source: Intel

Intel 14A: High-NA EUV Adoption Remains Uncertain

Intel also commented on 14A which is set for risk production in Oregon in 2027. 14A is expected to offer a 15-20% improvement in performance/ watt, 30% density gain, and 25-35% power reduction compared to 18A. At the same time, 14A will feature their 2^nd generation of RibbonFET and backside power delivery.

While some might claim that Intel is 1 year ahead of TSMC with 14A, 2028 is likely to be the year of mass production for 14A as 2027 is the year of risk production. We have seen how 18A has started risk production, but actual mass production tracks closely with TSMC.

Source: TSMC Technology Symposium 2025

For the 2^nd generation of backside power delivery, Intel has called it PowerDirect. PowerDirect is a more advanced form of backside power delivery network as it involves direct backside contact to the source/drain. This is like TSMC’s adoption of Super Power Rail for A16 in 2026. For 18A, Intel had adopted the Power Via method which is an intermediate solution between Buried Power Rail and Direct Contact.

Source: Applied Material

With regards to High-NA EUV, Intel made a comment that implies it is evaluating the cost effectiveness of introducing the new technology at 14A. Cost effectiveness is an important consideration for foundry. While High-NA EUV can reduce the number of process steps and simplify the process, the additional cost is still a hurdle for end customers. This is why I continue to believe that High-NA EUV adoption by TSMC will be more likely in 2030.

Intel’s roadmap still represents a few years delay in High-NA EUV adoption as Intel under Pat Gelsinger had previously mentioned about High-NA EUV involvement in production starting in 2025. Pat Gelsinger was too aggressive on being the 1^st to High-NA EUV when we have seen previous multi-years delay for Low-NA EUV adoption. High-NA EUV alone is not going to help Intel wins the foundry market.

Source: ASML and Intel joint announcement

This is a change in tone regarding to the adoption of High-NA EUV for 14A. Regardless, customers can proceed with their 14A design as it does not matter whether High-NA EUV will be adopted or not.

One of the differentiating factors on 14A is High-NA EUV tool. In Oregon, we have landed our second High-NA EUV tool. In fact, this tool came up much faster compared to our first one, and we are working in great collaboration with ASML. The tool is performing well to its expectations. I want to make 2 points for the audience today.

The first one is Intel still has the option to have either a low-NA or a High-NA solution on our 14A technology, and it's design rule compatible. There will be no impact to the customers depending on the path that we choose.

Second, the High-NA EUV is performing to the expectations, and we will introduce it at the right time. We already have data on 18A as well as 14A that shows yield parity between our low-NA-based solution and a High-NA-based solution. So we are continuing to make progress on the technology front and ensuring that we have the right options available for us to make sure the solution we deliver to our customers has the lowest risk and the best reward in terms of the decisions we make.

Advanced Packaging

Intel EMIB (Embedded Multi-die Interconnect Bridge) is a 2.5D advanced packaging technology that enables high-bandwidth, low-latency communication between multiple chiplets on a single substrate. Instead of using silicon interposer like CoWoS, it uses silicon bridge to connect the dies.

Intel announced the introduction of TSV (Through-Silicon Vias) capability for their EMIB technology with the EMIB-T solution. This is a more scalable solution, especially if AI clients wanted to add more HBM content.

Source: Intel

The other key advanced packaging solution of Intel is Foveros. Intel has introduced 2 new solutions, Foveros-B and Foveros-R, that will be production ready in 2027.

• Foveros-S uses silicon interposer and is in use for PC application

• Foveros-R uses RDL (redistribution layer) as a cost sensitive solution

• Foveros-B combines both RDL and silicon bridge for complex designs

Source: Intel

This is similar with TSMC’s 3 versions of CoWoS

• CoWoS-S uses silicon interposer and is adopted by NVIDIA’s Hopper

• CoWoS-R uses RDL (redistribution layer) as the interposer and is adopted by AWS’s Tranium

• CoWoS-L uses an interposer with a Local Silicon Interconnect (LSI) chip for die-to-die interconnect and RDL layers for power and signal delivery. This is adopted by NVIDIA’s Blackwell

Source: TSMC

The next advancement will be Intel’s Foveros Direct, which is their 3D stacking solution. Through die-to-wafer hybrid bonding, dies are bonded to the substrate wafer using copper-to-copper interconnect. Bond pitch smaller than 10 um can be achieved as compared to sub-25 um for Foveros 2.5D.

Source: Intel

Advanced packaging is an area that Intel is obviously still lagging TSMC by a few years. While TSMC has started to implement CoWoS-L for NVIDIA’s Blackwell in 2024, Intel’s Foveros-B will only be ready in 2027. In the area of hybrid bonding, TSMC’s SoIC has been in production since 2022 with pitch size as small as 6um in 2025.

Source: TSMC

Strengthening the Ecosystem

Intel also announced the formation of the Intel Foundry Chiplet Alliance and Value Chain Alliance, aiming to foster collaboration across the semiconductor ecosystem. Key EDA partners like Synopsys, Cadence and Siemens are working closely with Intel to develop certified design flows and IP for the 18A and 14A nodes. These collaborations are essential for ensuring a robust design environment for customers.

Source: Intel

It’s a smart move as Intel knows it can’t go it alone. And it’s borrowing a page from TSMC’s playbook by trying to create a collaborative ecosystem that makes it easier for customers to bring designs to tape-out. There is still lots for Intel to do to catch up with TSMC’s well known Open Innovation Platform.

Source: TSMC

Conclusion

If former CEO Pat Gelsinger was focused on getting Intel technologically ready for the foundry race, Tan Lip-Bu is now mastering the intricacies of the foundry business. Intel’s new CEO understands what it takes to succeed as a foundry and he’s beginning to speak the language of TSMC. Intel Foundry is emerging as a player to watch in the semiconductor foundry industry, even if it still faces clear disadvantages across several fronts.

You can also check out my recent article on TSMC 2025 Technology Symposium.

All slides below are from TSMC Technology Symposium. Here are the key takeaways that matter for both investors and industry watchers.

Semiconductor Market Outlook

According to TSMC, they continue to expect the global semiconductor market to grow by 10% in 2025. Similar to last year, Dr Kevin Zhang affirmed that the global semiconductor market will grow to $1 trillion by 2030. HPC/AI will account for 45%, followed by 25% for smartphone, 15% for automotive, 5% for IoT and 5% for others. Based on 2024 global semiconductor sales of $621 billion, this implies an 8.1% CAGR in the global semiconductor market from 2024 to 2030. 8.1% CAGR is the fastest the semiconductor market has grown since 2000.

The key driver behind the strong growth outlook is driven primarily by HPC/AI application. TSMC expects HPC/AI to be a $450 billion market by 2030. In the FY 2024 results call, CEO C.C. Wei believed that their revenue growth from AI accelerators will approach mid-40% CAGR from 2024 to 2029. This is after a 12x increase in wafer demand for AI accelerators from 2021 to 2025.

Currently, all AI customers (other than the Chinese) are working with TSMC on GPU and ASICs. Majority of AI accelerators demand is on 3nm and 5nm, using TSMC’s advanced packaging technology such as CoWoS and SoIC. In the chart below, we can see the scaling of training compute achieved by NVIDIA through leveraging the latest semiconductor technology.

The other major growth driver identified by TSMC is the automotive application which will become a $150 billion market by 2030. While the automotive market remains soft, silicon content is growing rapidly. Rising intelligence in automotive application and higher EV penetration is a boon for the automotive semiconductor market. A lot more sensors and computing power will be needed as cars are moving towards L3 to L5. Compute is also being centralized compared to the MCU dominant setup in traditional cars. Software defined vehicle is enabled by silicon defined vehicle. Use of 3nm for automotive computing and 12nm for MCU is quite a surprising development given the current process technology node used by automotive application.

Smartphone is a stable market given unit shipment has peaked in 2016. Content growth will be the key driver as Apple, Qualcomm and MediaTek continue to migrate to the next leading-edge node. AI smartphone could drive semiconductor content in the near-term, but we will have to wait for 6G in 2030 for a big jump in smartphone semiconductor content. For Wi-Fi, 6/7nm is required to achieve the latest technology of Wi-Fi 7. Image sensor is migrating from 28nm to 12nm, while RF is also migrating to 5/6nm

Both VR and Humanoid robot are new growth driver for global semiconductor market in the future. Many different type of semiconductors are needed to enable Humanoid such as sensor, PMIC, MCU, AP and connectivity. For VR to take off, semiconductor is required to drive 10x improvement in power, cost and form factor.

TSMC Technology Roadmap

Nothing surprising on TSMC’s roadmap with their dedication to small improvement in process technology on an annual cadence. N2 will start to ramp in 2025, followed by N2P and A16 in 2026. A16 is a version of N2 that will be equipped with Super Power Rail.

Similar to what TSMC has always done, they continue to improve on existing nodes and offer derivatives node that is more suitable for clients. TSMC has come up with N3X for client CPU, N3A for automotive and N3C for value product. Apple could be using N3C for its cheaper iPhone in the future. N3 has done really well for TSMC with revenue growth of more than 300% in 2024.

N2, which will adopt the new Gate-All-Around FET architecture, is set to ramp in 2H 2025. N2 will remain the industry leading process node, ahead of Intel’s 18A.

A16, which was introduced last year, will feature Super Power Rail. Super Power Rail is TSMC’s version of Backside Power Delivery (BPD) and is the hardest version of BPD. SPR is most suitable for AI/HPC product with high power requirement. OpenAI is rumored to be one of the early customers of A16 when it ramps in 2H 2026.

The number of new tape-out for N2 will grow a shocking 4x compared to N5 in the 2nd year. In addition to TSMC’s process leadership in N2, AI demand is likely the reason for the high number of tape-out. Google, Amazon, OpenAI, Meta and Microsoft should be looking at N2 node in 2027/28 to get a leg-up over NVIDIA. N2 is a very successful process node as TSMC has been in N3.

At the symposium, TSMC also introduced A14 as the next node that will enter mass production in 2028. This process builds on its nanosheet foundation and promises 10–15% performance gains and 25–30% power savings over N2. The logic density gain, speed improvement and power reduction of 14A are impressive although this is 3 years after the ramp of N2. However, the company will not include backside power delivery at A14. Instead, SPR will be offered as an option in 2029, a decision that diverges from Intel’s more aggressive adoption.

On High-NA EUV, it is unlikely that TSMC will adopt it for A14 due to cost and technology maturity issue. The likely timeline for TSMC to introduce High-NA EUV will be A10 node in 2030/31. However, A14 will see logic pitch shrink, so we are likely to see higher usage of multi-patterning with Low-NA EUV.

Comparing against N3E which was launched in 2H 2023, we can see that Super Power Rail is a great boost for TSMC’s A16 despite its higher cost.

Looking beyond A14, TSMC is already doing their research on future transistors innovation. While Moore’s Law has slowed, it is by no means dead. After GAA, we still have complementary FET (CFET) and High-NA to push the PPA further. The CFET architecture will stack both the n-type and p-type transistors on top of each other. ALD and etching providers will benefit in the transition to CFET architecture. Beyond CFET, TSMC is researching into future materials such as 2D transition metal dichalcogenides (TMD) and carbon nanotube (CNT).

Advanced Packaging Roadmap

Given a slowing Moore’s Law, advanced packaging is increasingly important to achieve further scaling. CoWoS (Chip on Wafer on Substrate) has become such an important term for investors looking at NVIDIA and AI demand in 2024. InFO is one of the key reasons why Apple has sole-sourced at TSMC in the last 10 years. TSMC’s head start in advanced packaging is becoming a barrier of entry for any competitors in addition to its front-end process leadership.

The company’s CoWoS platform continues to scale and TSMC expects to produce interposers up to 5.5x reticle size in 2026 and 9.5x reticle size in 2027. This will be able to integrate 12 HBM stacks alongside 4 AI accelerators. Rubin Ultra in 2027 is likely the 1st customer for this large package. Given that the package is now 9.5x reticle size, TSMC has also started to explore panel-level packaging solution to improve the yield rate.

Source: Data Center Dynamics

TSMC’s SoIC (System on Integrated Chips) platform will support 6um face-to-face hybrid bonding in 2025 and aims to enable A14-on-N2 chip stacking by 2029. The trajectory implies a 20x increase in I/O density in 2029 compared to the first SoIC generation. The growth of SoIC is important for BE Semiconductor investors as it will drive the adoption of hybrid bonder. AMD and Apple will use SoIC at N2 for their HPC application.

TSMC also introduces the SoW-X (System on Wafer) architecture, where wafer scale integration is achieved with CoWoS. The SoW-X platform promises over 40x the computing power of the current CoWoS package used by Blackwell and is slated for production by 2027. Unlike the current SoW-P platform which follows the chip-first approach, SoW-X will be using the chip-last approach. Companies such as Cerabras and Tesla’s Dojo have keen interests in SoW.

These architectural innovations are underpinned by a clear thesis that future performance scaling will come from advanced packaging. This is a distinct paradigm shift, and one that TSMC is leading with R&D, volume production and roadmaps. In addition, TSMC will also be introducing Co-Packaged Optics (CPO) to improve power efficiency and reduce latency of networking communication. Using photon in CPO is more energy efficient rather than electron in the current networking setup. Both Broadcom and NVIDIA are likely early adopters of CPO. TSMC is also seeking to introduce integrated power delivery in CoWoS for better power delivery density for AI application.

Source: Broadcom

Manufacturing Excellence

Dr. Cliff Hou, Deputy Co-COO and Chief Information Security Officer of TSMC, also presented on manufacturing excellence.

Defect density (D0) refers to the number of manufacturing defects found in a given area of a semiconductor wafer, typically measured in defects per centimeter square (defect / cm2). Lower defect density translates to higher yield and cost efficiency as there is higher proportion of usable chips per wafer. The trend of bigger die size also makes defect density more important as bigger die is more affected by higher defect density.

It was very impressive to hear that TSMC’s N2 defect density is better than N3 and N5 2 quarters before mass production. N2 defect density improvement is faster despite the move to the new GAA architecture.

Referencing the data released at the 2020 Technology Symposium, 5nm D0 is approximately 0.2/cm2. This put N2 D0 at less than 0.2/cm2. For reference, Intel said their defect density for 18A is 0.4 back in September 2024.

Source: TSMC Technology Symposium 2020, anandtech

Conclusion

The symposium offered not just a roadmap, but a masterclass in execution. TSMC’s measured approach to node migration reflects a foundry business driven by engineering discipline over marketing hype. Customers are not after the most fancy nodes, but wants a reliable node migration that will not lead to delay in their roadmap.

The heavy emphasis on advanced packaging innovation and leadership shows how TSMC is ahead of its peers in shaping the future of semiconductor innovation.

For those unfamiliar, Advantest is the sole provider of final testers for NVIDIA’s Blackwell chips. The high-end tester market is dominated by Advantest and Teradyne, with Advantest gaining share in recent years thanks to its strength in AI-related testing.

In a potential sign of softening CoWoS demand, Advantest is now guiding for a flattish sales outlook for FY2025. While a stronger yen has a mid-single digit impact on revenue, the market was still expecting a much stronger growth trajectory for the year.

As far as the first half versus the second half guidance, usually, we don't have as much visibility into the second half just because most of the visibility we have is 6 months out. But we do see a stronger first half right now as we stand at this point in the year.

So as Doug just explained, there might be in comparison, first and half, the first half is going to be a little bit higher, and it will be a huge gap. And with regards to the gap, as Doug just explained, for the second half, there is - we don't have full visibility. There might be some uncertainties.

Source: Advantest

Advantest should see stronger demand in 2026 as Rubin will lead to longer testing time again. Tester company benefits when the product upgrade cadence is faster.

Pull forward demand

There is growing evidence of demand pull forward in specific segments like PCs and iPhones. While the additional pull forward demand is perhaps only about 10% in a quarter, it is significant for ex-growth categories such as smartphones and PCs.

Both Q1 and Q2 tend to be low seasons for iPhone suppliers as the 2nd half of the year is when builds begin for the new iPhone launch in September. According to numbers from Morgan Stanley, Apple’s Taiwanese supply chain partners reported sales growth of 33.5% in March which is much higher than historical growth. In Q2, Morgan Stanley also estimated iPad builds of 13 million +23.8% YoY and iPhone builds of 45 million +15% YoY.

Source: Morgan Stanley

For PCs, Counterpoint reported 6.7% YoY growth in Q1 2025 “driven by pull-ins in anticipation of US tariffs and growing adoption of AI-enabled PCs.”

HP and Dell, on the other hand, benefited from the US market pull-ins during the quarter, with 6% and 4% YoY growth respectively, and maintained their second and third places in Q1. We also found that the pull-ins happened for other major brands too ahead of the tariff uncertainty, leading to the market share further consolidating around major brands.

In an earlier article, I have mentioned the higher notebook shipment by the ODMs in Q1.

Notebook shipment by the ODMs in Q1 grew 3% YoY, which is 10% higher than seasonality. In particular, notebook shipment in March grew by 39% MoM. In fact, ODMs have already started to prebuild inventory since November after President Trump won the election. Both AMD and Intel have seen double digit growth for PC CPU shipment in Q4, which is much higher than flattish PC unit shipment.

Source: Counterpoint

The latest Federal Reserve Biege Book in April is seeing stronger sales of vehicles and other nondurables

Non-auto consumer spending was lower overall; however, most Districts saw moderate to robust sales of vehicles and of some nondurables, generally attributed to a rush to purchase ahead of tariff-related price increases. Both leisure and business travel were down, on balance, and several Districts noted a decline in international visit

Intel

While Intel’s Q1 results was a beat, the forecast for Q2 was weaker than expected as they expect a 2 to 12% sequential decline in revenue. Intel noted similar dynamics of early pull-in of notebook shipment by the ODMs since November 2024

Similar to Q4 2024, we believe Q1 revenue benefited from customer purchasing behavior in anticipation of potential tariffs, though it is difficult to quantify the magnitude.

Investors were also stumped at why Intel is capacity constrained at N7 instead of Meteor Lake and Lunar Lake. First sold in October 2022, it is rare to see demand for an older CPU exceeding that of the newer chip.

Greater demand from our customers for N-1 and N-2 products so that they can continue to deliver system price points that consumers are really demanding. As we've all talked about, the macroeconomic concerns and tariffs, have everybody kind of hedging their bets and what they need to have from an inventory perspective. And Raptor Lake is a great part

There are 2 reasons why Raptor Lake is of a cheaper cost structure than Lunar Lake, Arrow Lake and Meteor Lake.

1. Intel took a $3 billion write-off of Intel 7 in Q3 2024 under ex-CEO Pat Gelsinger

2. Both Arrow Lake and Lunar Lake are manufactured by TSMC, which has lower gross margin than internal products. Some of the chiplets in Meteor Lake are made by TSMC too

This also suggests that the king of CPU is fighting a fierce price war with AMD.

Comments from Intel also suggest that outsourcing to TSMC will continue in the foreseeable future. Now, we shall see if Intel will outsource server CPU to TSMC.

Michelle C. Johnston Holthaus

And so when you look at Nova Lake, really what we have done is we've optimized at the SKU level, the process node that we're going to use. And so when you look at Nova Lake, you'll see product both at TSMC and you'll see product internal to Intel. But when you look at the aggregate of Nova Lake, we will build more wafers on Intel process than we are on Panther Lake.

David A. Zinsner

I'd just add one other thing that just I come over the top of the organization on is we are going to continue to balance internal and external manufacturing of wafers. We do that because that's part of our capital strategy to maintain a reasonable capital intensity relative to the business.

New CEO Tan Lip-Bu’s restructuring effort is a step in the right direction by taking decisive steps to streamline the company’s operations and sharpen its focus. He is flattening the leadership structure so that all critical functions (including product, manufacturing, and G&A) report directly to him.

This change is designed to reduce layers of management and enable the CEO to work more closely with Intel’s product and engineering teams, ensuring faster decision-making and tighter execution. As part of this broader effort, Intel is also targeting significant cost reductions, with operating expenses expected to fall to $17 billion in 2025 and further to $16 billion in 2026. Fixing the cultural rot at Intel is important

Tan Lip-Bu

One of my biggest learning so far is that we need to fundamentally transform our culture and the way in which we operate. Organizational complexity and bureaucracies have been suffocating the innovation and agility we need to win. It takes too long for decisions to get made. New ideas and people who generate them have not been given the room or resources to incubate and grow. The unnecessary silos have led to bad execution.

In a message to Intel’s employees, Tan Lip-Bu said

I’ve been surprised to learn that, in recent years, the most important KPI for many managers at Intel has been the size of their teams. Going forward, this will not be the case. I’m a big believer in the philosophy that the best leaders get the most done with the fewest people. We will embrace this mindset across the company, which will include empowering our top talent to make decisions and take greater ownership of key priorities.

SK Hynix

The company delivered strong earnings growth, with gross margin expanding to 57% and operating profit increasing 158% YoY. While weaker memory prices had some impact, HBM now accounts for 40% of total revenue and an even larger share of operating profit.

Source: SK Hynix

Despite some suggestion that Samsung is expected to be qualified by Nvidia for 12-Hi HBM3e, this is still highly uncertain and not impactful even if it happens. Based on the production cycle and inventory build, it is too late for Samsung if they get qualified. SK Hynix is achieving 12-Hi HBM3e bit sales crossover in Q2, so Nvidia is already preparing inventory for GB300 shipment in 2026. Samsung is also not achieving good progress in 1c nm node, which they plan to use for HBM4.

SK Hynix now expects HBM demand to grow at 50% CAGR from 2024 to 2028. This does suggest some slowdown in HBM growth rate going forward.

HBM Growth Rate based on SK Hynix’s guidance

• 2024: 300% for SK Hynix

• 2025: 100% for SK Hynix

• 2026-28: 35% CAGR for industry

This should not be a surprise if you have paid attention to Nvidia at GTC 2025. Rubin is featuring 288GB HBM4 capacity which is similar to that of Blackwell Ultra. This will impact HBM equipment suppliers such as Disco and Camtek as sales growth normalized. For SK Hynix, they will still benefit from double digit ASP uplift with migration from HBM3e to HBM4.

Source: Nvidia

There are more mentions of pull-in demands and rush orders in the company’s commentary

To share our current ongoing discussions with customers regarding supplies, global customers are generally maintaining their planned memory demand, as previously discussed with us. In fact, some customers are even requesting short-term supply pull-ins to expedite their demand.

For IT consumer goods such as PC and smartphones, tariffs are on temporary hold for now. Additionally, from the perspective of end customers, there is a possibility that some of them may rush purchases before price increase, which could, in turn, stimulate replacement demand.

So in Q1, tariff policies were not finalized. As a result, while some pull-in demand from customers may be reflected in the results, it did not come in a significant way and the impact was relatively limited. So our Q1 DRAM shipment exceeded original projection, but not by a significant margin, and the increase was mostly limited to client products such as mobile and PC. In addition, we understand that customer inventory levels did not show significant changes either.

In Q1, demand in the NAND market for major applications remained weak due to seasonal factors. However, there were signs of preemptive purchasing, particularly for some channels and discrete products, mainly driven by tariff considerations and potential inventory reductions. Coupled with suppliers' production cutbacks, this resulted in a price increase, especially in the spot market. In Q2, following the announcement of tariff policies, uncertainties have increased around the recovery of demand, both for discrete products, where demand had increased in Q1, as well as for major applications.

The boom bust cycle is baked into semiconductor and it’s what makes the industry so beautiful, brutal and never boring. Cycle has been around since the industry existed more than 70 years ago and a downcycle occurs every 3 to 4 years. What makes cycle different for the semiconductor industry is that believer of Moore’s Law knows the industry will always grow to new height. Yes, the semiconductor industry has weathered over 15 downcycles, yet it remains firmly on track to hit $1 trillion in revenue by 2030.

Source: TSMC

Source: World Semiconductor Trade Statistics

There are 2 different drivers of semiconductor downcycle, but they are inherently a mismatch of demand and supply. Supply is inelastic, while demand fluctuates a lot more.

The first is a capacity cycle where fabs have to make investment decision a few years ahead of mass production. During boom period, strong demand gives fab the confidence to invest for the long term structural growth drivers of the industry. Everybody makes the same decision and starts to regret the situation of overcapacity when their capacity come online at the same time. Capacity cycle is a lot less common post GFC given the high level of consolidation in the industry. It still happens for more fragmented segments such as analog (TI), power discrete and SiC substrate.

The second driver is the inventory cycle, which occurs more frequently than the capacity cycle. This is also known as the bullwhip effect, where small changes in end demand can lead to increasingly amplified swings in orders and inventory levels up the supply chain. During periods of rising demand, customers restock and rebuild inventory. In times of shortage (such as during COVID), this can also lead to double ordering. But when demand slows, customers cut back sharply to clear the excess inventory, causing a sudden collapse in new orders. An example is as such:

1. End demand changes slightly, for e.g. a 3% drop in smartphone sales

2. OEMs react conservatively, cutting chip orders by 7% to adjust inventory.

3. Distributors pull back more, fearing excess stock and cut orders by 15%.

4. Foundries see a sharp drop, leading to lower utilization rate and margin pressure.

Source: Sketchplanations

A downcycle occurs when global semiconductor sales growth peaks and begins to decelerate (i.e. January 2018 and December 2021), triggering an inventory correction across the supply chain. Once sales growth peaks, it often has a tendency to swing hard towards flat or negative region.

Source: WSTS Global Semiconductor Sales from 1987 to 2025

While situation is still fluid, we are likely approaching the next downcycle in a few months based on the latest tariff development. My prediction is that global semiconductor sales growth will peak in Q3 2025 for the following reasons:

1. U.S. tariff leads to demand shock

2. Pull forward demand

3. AI: Inventory correction and softer capex growth in 2026

U.S. Tariff Leads To Demand Shock

On 2nd April 2025, President Donald Trump declared "Liberation Day" unveiling a sweeping tariff regime aimed at reshaping global trade dynamics. Invoking a national emergency, he imposed a universal 10% tariff on all imports, with significantly higher "reciprocal" tariffs targeting specific countries: 34% on China (raising the total to 54%), 32% on Taiwan, 25% on South Korea, and 20% on the European Union, among others. The announcement triggered immediate global backlash and market turmoil. China retaliated with tariffs of up to 125% on U.S. goods, while the current tariffs on China stands at 145%.

Source: CNN

On 9th April, the Trump administration signaled potential exemptions and a 90-day pause on reciprocal tariffs to facilitate trade negotiations, though the tariffs on Chinese imports remained in effect. Few days later, it was revealed that the U.S. Customs and Border Protection agency has exempted certain electronics products such as smartphone, PC, network equipment from reciprocal tariff. As it stands today, these are the current tariff rate according to Foxconn:

Source: Foxconn

However, this is not over yet as the reciprocal tariff exemption is merely shifting these electronics product to be evaluated under a separate semiconductor tariff. On 14th April, it was revealed that the Department of Commerce has launched a probe on semiconductor tariff under Section 232 of the Trade Expansion Act of 1962. Therefore, it is highly likely that semiconductor and electronics products will be subjected to a future tariff irrespective of the deals that countries may have struck with President Trump. We know that as steel, aluminum and automotive have been subjected to Section 232 duties even if they are from Mexico or Canada.

Source: White House

Source: Federal Register

​Tariffs directly influence demand by altering prices, compelling companies to either pass increased costs to consumers or absorb them. As prices rise, demand typically declines, adhering to the law of demand. The extent of this impact on semiconductor varies across different verticals.

Source: Economics Help

Personal Computers (PC): The U.S. accounts for approximately 25% of global PC unit sales and 30% of PC value sales. Margin for PC OEMs is low, which will force them to pass on higher cost to the end consumers. In addition, 80% of global notebook assembly capacity is located in China, where China will slap a 125% tariff on Made-in-USA Intel chip and U.S. will slap another layer of tariff on China imported PC. This makes PC the most vulnerable vertical to tariff. Most of the OEMs do not plan to set up assembly plant for PC in the U.S. and have decided to further expand their capacity in ASEAN.

Smartphones: The U.S. represents about 10% of global smartphone unit sales and 20% of value sales. However, U.S. is 40% of Apple’s sales as it holds more than 50% market share in the country. This makes Apple more vulnerable than Android smartphone, which is not a good news as iPhones tend to have much higher semiconductor content than the average Android smartphone.

Servers: Server demand has less direct impact from the tariff as the ODMs have plenty of capacity in Mexico and U.S. TSMC’s Arizona Fab 21 has started mass production of 4nm, which is precisely the node that Blackwell is made.

Memory: Most of the memory manufacturing sites are located outside of U.S. in countries such as Korea, Japan, Taiwan and Singapore. Many of the memory modules and SSDs are also assembled outside of U.S. Even for Micron, they relied heavily on their NAND factory in Singapore and DRAM factories in Taichung & Japan. Their new Idaho fab will only contribute meaningful supply in 2027. Price elasticity for memory (especially NAND) is high which should lead to lower demand.

Pull Forward Demand

Pull forward demand is bad for semiconductor as it creates a high base and leads to lower demand in the future. An example is the elevated PC annual sales of >300 million units during the Covid period of 2020 to 2022, above the historical average of 260 to 270 million units. In 2023, PC shipment fell by 15% YoY to 242 million units, which is the lowest unit shipment since 2006. From the peak in 2021, unit shipment fell by 30% in 2 years.

Two sources of pull forward demand have emerged, which will put pressure on sales in 2026.

1. China consumer electronics subsidies

On January 20, 2025, China officially launched a national subsidy program for smartphones, tablets and smartwatches. The government offers a 15% discount on smartphones priced below RMB 6,000, capped at RMB 500 per device. This initiative aimed to stimulate consumer electronics demand and was part of a broader effort to boost domestic consumption. Notably, some provinces, such as Jiangsu, had already implemented similar subsidy programs as early as November 2024. The subsidies led to a significant uptick in smartphone sales. In January 2025, China smartphone sales grew by 17% YoY and 41% MoM to 29 million units. Combining with February, China smartphone sales grew by 13% YoY. Total Electronics & Appliances sales in China grew 35.1% YoY in March.

Source: Counterpoint Research

2. Tariff induces pull forward demand during the 90-day pause

Following President Trump's announcement of sweeping tariffs on imports, a 90-day pause was granted for most countries, excluding China, to allow for negotiations and adjustments. This temporary reprieve prompted both businesses and consumers to accelerate purchases of goods, particularly high-value electronics, to avoid potential price increases once the tariffs were reinstated.

Above seasonal sales strength has been seen across multiple verticals. U.S. new vehicle sales grew 4.8% YoY in Q1. According to IDC, global PC sales grew by 5% YoY in Q1 of which Macbook sales grew by 14% yoy. These are Q1 sales where the world is not aware of the big tariff spike. Post Liberation Day, panic buying should have accelerated especially with the 90-day pause.

Source: Apple

For corporates, the 90-day pause is the best opportunity for them to stock up on electronics before reciprocal tariff resumes or Section 232 tariff is implemented for semiconductor. Reuters reported that Apple had airlifted 600 tons of iPhones from India to beat the tariffs. Morgan Stanley raised their Q2 iPhone build by 10% to 45 million units, which is 5 to 15% higher than typical seasonality (destocking to prepare for the new iPhone model in September).

Notebook shipment by the ODMs in Q1 grew 3% YoY, which is 10% higher than seasonality. In particular, notebook shipment in March grew by 39% MoM. In fact, ODMs have already started to prebuild inventory since November after President Trump won the election. Both AMD and Intel have seen double digit growth for PC CPU shipment in Q4, which is much higher than flattish PC unit shipment.

​Despite elevated channel inventories, retailers and distributors are seizing the opportunity to stock up on tariff-exempt smartphones and PCs during the current reprieve. This is a temporary window of opportunity to secure inventory at lower costs. However, even if tariffs are eventually lifted, the accumulation of high channel inventory typically leads to a subsequent destocking phase.

AI: Inventory Correction, Softer Capex outlook and Geopolitical risk

1. Inventory Correction

By now, most should be familiar with the issues plaguing GB200 rack deliveries. GB200 server rack production is currently facing significant challenges due to assembly yield issues, particularly at the ODM level (Foxconn, Quanta, Wiwynn). The complexity of the GB200 NVL72 systems, which integrate 72 GPUs and 36 Grace CPUs per rack, has led to difficulties in the assembly process. These challenges have resulted in lower than expected rack shipment volumes, with estimates for 2025 reduced from an initial 50,000 racks to approximately 15,000 racks. GB300 is also facing assembly yield issues as delivery timeline has been pushed to Q1 2026.

Despite ongoing assembly challenges with NVIDIA's GB200 racks, NVIDIA's revenue outlook for the first half of 2025 remains robust. This resilience is largely due to NVIDIA's revenue recognition policy, which records sales upon the shipment of GB200 boards to ODMs, rather than upon the final delivery of assembled racks to end customers. Consequently, delays in rack assembly have led to an accumulation of inventory at the ODMs, without immediately impacting NVIDIA's reported revenues.​ TSMC has been shipping out Blackwell since November while the ODMs revenue growth has lagged. The true extent of inventory build will only be known when the ODMs report their financials over the next few quarters.

However, this inventory buildup is unsustainable for the ODMs. Operating on thin margins and facing significant working capital requirements (given the high value of GB200 components), ODMs are under financial strain. To manage these pressures, many have resorted to funding strategies such as issuing convertible bonds and GDRs to bolster their capital in 2024. Wistron is in the plan to issue 250 million new shares in GDR. While these measures provide temporary relief, the continued accumulation of unsold GB200 inventory could lead to ODMs deciding not to increase their GB200 inventory. This is perhaps why CoWoS demand forecast has been revised down. If rack delivery issues remain unresolved, there will eventually be wafer order cut from Nvidia.

2. Weaker sales outlook for FAMG and elevated capex intensity

The ongoing trade war does not bode well for companies such as Meta, Amazon and Alphabet. Meta and Alphabet are heavily reliant on advertisement sales which is highly correlated to the state of the economy. Both Temu and Shein have significantly reduced their advertising spend on Google and Meta platforms. Meta’s share price has since declined more than 33% from its February peak. Meanwhile, over 50% of Amazon’s third-party sellers are based in China, highlighting the platform’s exposure to the ongoing trade war between China and U.S.

Source: Adweek

Source: SMEC

Capex intensity (capex-to-sales ratio) is now at an all-time high, putting pressure on free cash flow. FAMG are expected to spend 50-70% of their operating cash flow on capex in 2025. Capex can rise either through revenue growth or higher capital intensity. In 2024 and 2025, the sharp spike in capex spending by the FAMG has led to a notable decline in free cash flow. Historically, during periods of economic uncertainty or slower growth, the FAMG have responded with inventory digestion or capex moderation, as seen in 2019 and again in early 2022.

Before ChatGPT’s breakout in late 2022, there was an earlier wave of AI enthusiasm sparked by AlphaGo’s 2016 victory over Lee Sedol. During that period, shares of SK Hynix and Micron surged over 300% from 2016 to their 2018 peak, while Samsung had already begun mass production of HBM.

Source: Micron in 2018

In 2019, a slowdown in revenue growth prompted capex reductions across the FAMG group. This also coincides with the trade war that President Trump started in his 1st presidency. Meta cut its capex guidance twice, lowering it from an initial $18–20 billion to $16–18 billion, as sales growth decelerated due to user saturation in the U.S. and the impact of GDPR in Europe. Alphabet also saw a significant moderation in capex following its slowest quarterly sales growth since 2015. For Microsoft, capex growth moderation reflected a digestion phase after heavy infrastructure investments in the past 2 years.

In 2022, FAMG cut capex in response to a sharp slowdown in revenue growth and rising macroeconomic uncertainty. Soaring inflation, interest rate hikes, and weakening consumer demand prompted a shift from aggressive expansion to cost discipline. Meta and Alphabet scaled back infrastructure and hiring plans, while Microsoft and Amazon focused on optimizing existing capacity after years of elevated investment during the pandemic driven digital surge.

While the FAMG have committed to their capex plans for 2025, the announcement of Liberation Day has reintroduced uncertainty into the economic outlook. Any meaningful hit to revenue growth could lead to a moderation in capex expansion in 2026. Long-term investment in AI remains intact, driven by the continued validity of the 3 Scaling Laws. However, digestion periods like those seen in 2019 and 2022 can still occur, even in the presence of transformative technologies like convolutional neural networks (CNNs) and Scaling Law (Kaplan, 2020).

3. Geopolitical risks and regulations

There are also additional geopolitical risks such as the recent ban of NVIDIA’s H20 shipment to China. NVIDIA has to take a $5.5 billion charges with revenue impact of at least $10 billion. ​In January 2025, the Biden administration introduced the AI Diffusion Rule, a comprehensive export control framework aimed at regulating the global distribution of advanced U.S. AI technologies. AI Diffusion Rule is set to be take effect from 15th May 2025 if it is not reversed by the Trump administration. This will have a big impact on GPU demand coming from Sovereign AI across Asia and Middle East.

Silver Lining In The Dark Cloud

While the dark cloud has gathered, several factors suggest that we do not have to be overly pessimistic of semiconductor companies. This is because market always looks forward for semiconductor stocks. To put it in another way, semiconductor stocks often bottom ahead of the bottom in semiconductor sales growth.

1. The market has partially priced in a certain degree of downcycle

In past upcycles, share price corrections typically occurred only after global semiconductor sales growth peaked and began to decline. This time, however, SOXX peaked early in July 2024, even as the 3-month moving average of global semiconductor sales growth has remained elevated.

The current 37% drawdown in SOXX is already approaching the 49% seen during the 2022 downcycle. While historical drawdowns aren't always directly comparable, it's worth noting that the sector saw much deeper declines of 60-70% following the Dot-Com Bubble and the 2008 Global Financial Crisis. Conversely, corrections were more modest at more than 30% during the 2018 and COVID downturns, when macroeconomic conditions were relatively more benign.

2. Asynchronous cycles across semiconductor verticals

What makes this cycle unique is the lack of synchronization across semiconductor verticals. Smartphones, PCs, and memory were the first to correct in 2022 and also the first to rebound in 2023. The strength of the current upcycle has been driven almost entirely by AI related demand, while most other end markets remain sluggish. Notably, automotive semiconductor companies are still working through inventory corrections nearly three years after SOXX peaked in December 2021! It is more appropriate to say there are multiple cycles within the different verticals.

This means that certain segments may bottom earlier than others. Using peak-to-trough drawdowns as a guide, semiconductor equipment companies have seen declines of 40–50%, driven largely by concerns over their China revenue exposure. Lower valuations are a positive for semicap, as the Big Four allocate a significant portion of their free cash flow to do share buybacks. Meanwhile, share prices of analog semiconductor companies are approaching their 2023 lows, reflecting their high sensitivity to weakness in global industrial and automotive demand although they are already under-shipping actual demand.

On the other hand, AI related stocks have slightly outperformed the broader SOXX drawdown, with shares of Broadcom, NVIDIA, and TSMC declining around 33%. Historically, however, it’s often the hottest theme of the upcycle that faces the sharpest correction in a downcycle. Again, think about the carnage for automotive semiconductor companies after the 2021 shortage cycle.

In both the 2018 and 2022 downcycles, NVIDIA’s share price fell over 60% from its peak. Jensen has historically opted for steep inventory charges over price cuts, an action that has often marked the bottom in NVIDIA’s share price in 2019 and 2022. While the $5.5 billion charge helps to clear the Hopper inventory risk, we need inventory charge on Blackwell.

Meanwhile, TSMC’s ADR is still trading at a 15% premium to its Taiwan listed shares (2330.TW). The gap narrowed to nearly 0% at the stock’s bottom in Q3 2022. TSMC has just reaffirmed its full-year guidance for 2025, but is it a bottom when the world’s most important foundry hasn’t even cut guidance yet? We have also not seen any downward guidance revision from Broadcom and NVIDIA.

​A slowdown in AI capex poses significant challenges for DRAM manufacturers. HBM3, for instance, consumes approximately three times the wafer capacity of DDR5 owing to its larger die size and lower yield rates . This shift has led companies like Samsung, SK Hynix, and Micron to allocate more wafer capacity toward HBM and reducing the available supply for DDR5. The recent U.S. export ban on Nvidia's H20 AI chips to China is expected to reduce their revenue by about 1%, but it could lead to a 3% increase in DRAM bit supply as wafer allocations revert from HBM back to standard DDR5 module . This reallocation may exacerbate oversupply issues in the DRAM market, potentially impacting pricing and profitability for manufacturers.

3. Investment thesis for AI is intact as Scaling Laws remain

Today, we have three Scaling Laws in AI: Pre-Training Scaling, Post-Training Scaling, and Test-Time Compute Scaling. While Pre-Training Scaling may be nearing its limits in a few years, the latter two remain highly promising. As models grow, emergent properties continue to surface which reinforces the case that more compute remains a viable path to breakthroughs in AI capabilities.

Source: Jensen Huang at CES 2025

This dynamic also feeds into Jevons Paradox: as AI becomes more powerful and cost-efficient, its utility rises, spurring even greater usage rather than reducing demand. The emergence of AI agents further amplifies this trend, as their ability to automate tasks, generate outputs, and interact with other systems autonomously creates exponential demand for inference compute. AI agents are expected to improve significantly and achieve adoption readiness by the end of the year. The long-term investment thesis for AI remains intact, as it has since 2016. However, this doesn't preclude painful digestion periods like those seen in 2018 and 2022 from occurring along the way.

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Conclusion

The semiconductor industry is no stranger to cycles and that’s exactly what has captivated me so deeply. Its inherent cyclicality is driven by capacity mismatches, inventory imbalances and unpredictable demand shocks. While the current cycle is shaped by unprecedented geopolitical developments, AI driven optimism, and asynchronous recoveries, it echoes the same dynamics that have defined the past 70 years.

As we head into what appears to be another downcycle, investors must brace for further turbulence while keeping their eyes on the long arc of technological progress driven by Moore’s Law. The road to $1 trillion in semiconductor industry revenue by 2030 will not be linear, but it is a path worth navigating. Lower valuations and falling share prices are often healthy first steps toward an eventual bottom.

For investors, the best way to prepare for the coming semiconductor downcycle is to stay focused on high-quality companies positioned to benefit from strong structural tailwinds once the industry recovers. If you find the content is useful, do subscribe to discover global semiconductor leaders worth owning for the next cycle.

BYD was founded in 1995 as a battery manufacturer and quickly became a global leader in the rechargeable battery market. The company entered the automotive industry in 2003 by acquiring Xi’an Qinchuan Automobile Company. Leveraging its strength in battery technology, BYD pivoted toward electric mobility, becoming one of the earliest Chinese producers of Electric Vehicle (EV or known as NEV in China).

When looking at power semiconductor, it is important to understand BYD as it is the largest EV producer globally. In 2024, BYD delivered 4.27 million electric vehicles (both battery electric vehicles [BEVs] and plug-in hybrid electric vehicles [PHEVs]), accounting for approximately 25% of global EV shipments. This figure is also 2.5 times more than Tesla’s 1.7 million units. China is the biggest EV market globally as it accounts for 65% (11.2 million units) of the global EV sales (17.1 million units).

BYD is bold in its EV strategy and is instrumental in shaping the direction of China’s NEV industry. In 2022, it became the first in China to go all-in on NEVs as it discontinue production of internal combustion engine vehicles (ICE). In 2025, it announced the adoption of advanced driver-assistance system (ADAS) for all its EVs.

BYD’s vertical integration is a major competitive advantage that underpins its leadership in the global EV market. Unlike most automakers, BYD produces nearly all critical components in-house: batteries, electric motors, semiconductors, vehicle platforms, and even the software that powers its cars. It owns BYD Electronics, which is a listed company that acts as a Tier 1 OEM for BYD. BYD is known to procure up to 70% of components from its in-house subsidiaries. This level of vertical integration is high than Tesla which still relies on external partners for batteries and semiconductor.

In addition to its scale, vertical integration allows BYD to become the lowest cost producer. The status of lowest cost producer is critical for BYD to offer the most competitive pricing in the world. It can also drive a faster innovation cycle as we have seen with Blade Battery and DM-i hybrid system.

Let’s take a closer look at BYD Semiconductor, one of BYD’s most important subsidiaries after its battery arm, FinDreams Battery.

Table of Content

• History of BYD Semiconductor

• BYD Semiconductor Portfolio

  • Power Discrete and Module

  • Smart Control IC

  • Sensors and Optoelectronics

• What else will they do in the future?

• Implication for Global Power Semiconductor

History of BYD Semiconductor

BYD Semiconductor was first established in 2002 as a fabless design company to research on battery protection IC. This was a year before it decided to went into the automotive sector in 2003. Subsequently, it also went into microelectronics, optics and LED.

In 2004, TSMC made the decision to shut down Fab 1. This was the company’s very first fab, originally located inside the Industrial Technology Research Institute (ITRI) where TSMC was founded in 1987. In 2005, all the equipment from TSMC’s Fab 1 was sold off as a complete line to establish a 6-inch fab at Ningbo SinoMOS Semiconductor (宁波中纬). Ningbo SinoMOS’s patents were mainly licensed from TSMC. Many of their engineers were also former TSMC employees, so there were some similarities in process technology and management.

Facing financial difficulties, BYD came in to acquire Ningbo SinoMos in 2008 for $29 million. They knew that IGBT will be a key component for electric vehicle. This is how BYD Semiconductor went from a fabless company to an integrated device manufacturer (IDM) that oversees the entire production process from design to manufacturing. In fact, BYD is also a system company that incorporates the chip made from BYD Semiconductor in its EVs.

Source: Samsung

BYD Semiconductor Portfolio

With more than 20 years of history, BYD Semiconductor has a wide product portfolio that can be broadly categorized as Power, MCU, Sensor and Optoelectronics. This can cover most of the semiconductor requirement in an EV other than infotainment SoCs and autonomous driving processors. While BYD Semiconductor has centered its strategy around automotive application, its products are also used in industrial, home appliances, consumer electronics and renewables.

Source: BYD Semiconductor

These are the known subsidiaries of BYD Semiconductor

1. BYD Ningbo Semiconductor

   1. Based in Ningbo

   2. The foundry that BYD Semiconductor acquired in 2008. Original equipment and process was from TSMC

   3. First production base for IGBT 4.0

2. BYD Changsha Semiconductor

   1. 8-inch plant that started mass production in 2022

   2. Annual capacity is able to fulfil the chips requirement for 500,000 cars

3. BYD Xi’An Semiconductor

   1. Based in Xi’An, which is also BYD’s largest EV production base

   2. R&D Center and the production base for IGBT 6.0

4. BYD Yangzhou Semiconductor

   1. Based in Yangzhou, Jiangsu

   2. Production site for DM-i 4.0 IGBT module

5. BYD Chengdu Semiconductor

   1. Started construction in 2022

   2. 12-inch IGBT fab

6. BYD Shaoxing Semiconductor

   1. Started production in 2023

   2. Production of Power and optoelectronics

7. BYD Jinan Energen Semiconductor

   1. Based in Jinan, Shandong

   2. Producer of 8-inch silicon and silicon carbide (SiC)

   3. Acquired in 2021 with Jinan government owning a minority stake. Foxconn was a former investor when it was founded in 2018

8. Guangdong BYD JieNeng

   1. Based in Huizhou

   2. Focus on optoelectronic semiconductor products such as LED lighting, optoelectronic modules and smart security

Power Discrete and Module

Of all the major product categories, Power Discrete is the most important for BYD both strategically and financially. Many of BYD’s innovations in its EVs would not have been possible without the support of BYD Semiconductor as the power semi content in EV is up to 5x higher than ICE. Products in this segment includes IGBT chips/modules, IPM modules, FRD chips, and SiC devices.

Source: Infineon

Fast Recovery Diode (FRD) is a semiconductor component designed to rapidly switch off after conducting current in order to minimize power loss and heat generation. Unlike standard diodes, FRDs have a much shorter reverse recovery time, making them ideal for high-speed switching applications such as inverters and motor drives. FRD is important in automotive where energy efficiency and thermal management are critical. BYD Semiconductor FRD chips can cover a voltage range of 650V to 1200V.

Insulated Gate Bipolar Transistor (IGBT) is commonly used in power electronics for switching and amplifying electrical signals. It combines the high efficiency and fast switching capabilities of a MOSFET with the high current and low saturation voltage handling of a bipolar transistor. This makes IGBT ideal for medium- to high-voltage applications such as inverters, EV motor drives and renewable energy systems.

EV is driving strong demand growth for IGBT as every EV requires multiple IGBT modules for motor inverters, on-board chargers, etc. IGBT is crucial in EV powertrains to efficiently convert DC power from batteries into AC power to drive electric motors.

Source: Yole

BYD Semiconductor formed a team to do R&D on IGBT back in 2005. The first IGBT 1.0 chip was launched in 2009, followed by the IGBT 2.0 chip in 2012 and the IGBT 4.0 chip in 2018. Although it still lags behind international peers, the IGBT 4.0 chip incorporates a planar gate design that reduces overall power losses by approximately 20% and increased temperature cycle life by more than 10 times. In 2020, the IGBT 5.0 chip was produced based on the high density Trench FS technology. IGBT 6.0 chip was released in 2022 and BYD Semiconductor is no longer that far away in technology from the likes of Infineon. Today, BYD Semiconductor is the largest domestic supplier of IGBT for automotive in China.

One of the key reason for BYD’s share gain in the recent years was the launch of the Dual-Mode Intelligence (DM-i) solution for its PHEV. DM-i 4.0 was first introduced in 2021 with a fuel efficiency of 3.8L/100km and cost parity with ICE. Unlike other hybrid system, DM-i will prioritize the use of electrical power which reduces fuel consumption. One of the core components of the DM-i 4.0 system is the Electric Hybrid System (EHS), which incorporates BYD's in-house IGBT 4.0 chip, enabling the electric control system to achieve an efficiency of up to 98.5%. The DM-i 4.0 IGBT module integrates the power drive, generation and buck/boost units into a single package, optimizing structural layout for a high degree of integration. This exemplifies how vertical integration and close collaboration with BYD Semiconductor enable BYD to achieve breakthroughs in its EV technology. Cost savings were also achieved through vertical integration, as the IGBT represents a significant portion of the EHS's overall cost. In 2024, DM-i 5.0 was introduced which reduced fuel consumption by 25% to 2.9L/100km and improved the range by 50% to 2100km.

Source: BYD

Silicon Carbide (SiC) is a wide bandgap semiconductor material that offers superior efficiency, higher thermal conductivity, and faster switching capabilities compared to traditional silicon. In EV, SiC is increasingly adopted for inverters, onboard chargers, and DC-DC converters where it enables more compact systems with reduced energy loss. Its ability to operate at higher voltages and temperatures makes it ideal for improving the overall efficiency and driving range of EVs, while also contributing to faster charging and better performance.

Source: DISCO

The main setback for SiC adoption is that it is much more expensive than traditional silicon. This is due to the complex and costly manufacturing process, which involves growing high quality SiC crystals. SiC is grown using a method called sublimation, which is more complex than the Czochralski method used for silicon wafer. As wafer size increases from 6-inch to 8-inch, maintaining crystal uniformity and minimizing defects across a larger area becomes much harder.

Additionally, SiC wafers are harder (Mohs hardness of 9.5 compared to 7 for Silicon) and more brittle, making them more difficult to process and resulting in lower yield. Wolfspeed has faced lots of difficulty in ramping its 8-inch Mohawk fab.

BYD Semiconductor had invested in SiC research for years and first introduced their three-phase full-bridge 1200V 840A SiC module for motor drives in 2020. In 2022, they released a 1200V 1040A SiC module that boosted power by 30% for their 800V platform.

1200V SiC HPD module, Source: CNEVPost

On March 17, 2025, BYD launched its groundbreaking Super E Platform, marking a significant leap forward in EV charging technology. The platform introduces a 1000V architecture and supports a peak charging power of 1 MW. With this advancement, BYD enables a fast charging rate of up to 10C (fully charging a 100 kWh battery in 6 minutes), compared to the current industry level of 6C. With its ultra-fast charging, Super E Platform vehicles can reach 2 km of range per second, or up to 400 km of range in just 5 minutes.

Source: BYD

This achievement was made possible by BYD Semiconductor breakthrough in high-power 1,500V SiC chips. It marks the first large-scale application of 1500V SiC chips in the global automotive industry. Through the use of laser welding technology, parasitic inductance has been reduced to 5 nH, and current capacity increased to 1000A. At the module level, it has shifted from the traditional HPD module to a half-bridge DCM architecture (compare the 1500V module below with the 1200V HPD module earlier). Double sided silver sintering is also used to enhance the thermal (Up to 200°C) and electrical performance.

Source: BYD

According to tphuang (very good source for BYD), BYD Semiconductor is working on 1700V SiC module which will enable >1000V platform. 1 advantage of BYD Semiconductor in China is that it is vertically integrated across the supply chain from the epitaxy growth to the final module. Unlike global players, Chinese companies are mostly involved in only 1 to 3 steps of the SiC manufacturing process.

Source: Knowmade

Smart Control IC

The core products under the Smart Control IC segment are MCU and PMIC.

Microcontroller Unit (MCU) is an integrated circuit that contains a processor core, memory, and input/output peripherals on a single chip. In a way, it is a simpler form of CPU that acts as the "brain" for controlling specific functions within electronic systems.

In the automotive industry, the use of MCUs is rapidly increasing due to the growing complexity and rising penetration rate of EV. From basic body control modules (like windows, lights, and wipers) to advanced driver-assistance system (ADAS), battery management system (BMS), motor control, and OTA updates, MCUs are essential for EV and intelligent cars.

BYD Semiconductor started to offer industrial-grade MCU in 2009 that can integrate functions such as control, RFID, capacitive touch sensing, and LED driving. They are adopted in small appliances like microwave, induction cookers and smart door locks.

BYD Semiconductor then extended its business to automotive MCUs and launched the first generation of 8-bit automotive MCU in 2018, followed by 32-bit automotive MCU in 2019. 8-bit MCU is simpler, cheaper, and typically used in basic control tasks like window, lighting, and seat adjustment. In contrast, 32-bit MCU offers much higher performance and are used in complex systems such as engine control unit (ECU), ADAS and BMS in EV.

In EV, precise control is required for the charging / discharging behavior, thermal status, and cell balancing of the battery. This is done through the BMS that processes data collected (current, temperature) and calculates the State of Charge (SOC). BMS is also able to increase the lifespan of the battery and ensures its safety. Reliability is important and BYD Semiconductor has achieved AEC-Q100 Grade 0 (temperature tolerance of up to 150°C) for its MCU. In 2021, BYD Semiconductor has shipped out more than 10 million units of MCU.

BS9046AM64 Block Diagram based on ARM Cortex-M4F core, Source: BYD

PMIC (Power Management Integrated Circuit) is a specialized chip that manages the distribution, conversion and sequencing of electrical power within electronic systems. In EV, PMICs play a critical role in ensuring efficient and stable power delivery across a wide range of subsystems with varying voltage and current requirements.

BYD Semiconductor started to supply battery protection IC for top-tier international phone brands as early as 2007. It also has AC-DC products that are primarily used in smartphone, laptop, networking device and smart home application. Most of the AC-DC converters are not automotive grade. For DC-DC converter, I can only find a single product BF1231. This is a relatively weaker product portfolio within BYD Semiconductor as compared to power discrete and MCU. Automotive is a relatively high-end product for TI and ADI.

Source: BYD

Sensors and Optoelectronics

BYD Semiconductor’s sensor line includes CMOS image sensors (CIS) for cameras (used in surround view systems, rear cameras and driver monitoring) and other sensors like magnetic position sensors (used in motors or pedals). The automotive CIS market is growing thanks to ADAS adoption as the number of cameras per car is increasing (rear camera mandated in many markets, plus front and side cameras for ADAS). BYD Semiconductor serves the automotive market with a range of CIS from VGA to 2MP, 3MP and 8MP. Current adoption rate is still mostly for driver monitoring in the car interiors. BYD Semiconductor also supplies low-end CIS for the smartphone and surveillance industry.

Source: BYD

Electromagnetic sensors convert physical quantities such as current, position, and pressure into standardized or application-specific electrical signals. They primarily include current sensors and angular position sensors. The company’s current sensors support a wide measurement range from 100A to 3,500A, while its angular position sensors achieve a detection accuracy of up to 0.05 degrees.

Optoelectronic Semiconductors includes LED lighting and display IC (LED drivers or small display ICs). This is a relatively mature market for BYD which allows BYD to cost down with BYD Semiconductor. Shaoxing plant is able to supply up to 6 billion optoelectronic units annually. Automotive LED products include Light Source, Smart Lighting, In-Vehicle Display and Intelligent Display.

One interesting product is the Far and Near Infrared Night Vision System, which offers advanced capabilities such as:

1. Pedestrian and vehicle detection and identification

2. Clear imaging at night, enabling visibility through darkness, glare, and haze

3. Glare suppression for oncoming vehicle headlights

This system significantly enhances driving safety and situational awareness, especially in low-visibility environments.

What else will they do in the future?

Recently, BYD founder Wang Chuanfu said that he would like to expand BYD Semiconductor from 5000 people to 8000 people.

It is also known that BYD is working on infotainment chip and ADAS chip in the future. Currently, BYD relies on Nvidia’s Orin, Black Sesame and Horizon Robotics for its ADAS solution. BYD ADAS chip is said to be able to achieve a performance of 80 TOPS which is still lower than its suppliers. Qualcomm is currently the market leader for infotainment chip in automotive.

Last year, BYD Semiconductor also said that they had open the world’s largest SiC fab that is 10x bigger than the 2nd largest SiC fab. That is a lot of capacity entering production!

Implication for Global Power Semiconductor

The rise of BYD and BYD Semiconductor is bad news for the global power semiconductor suppliers. Before I elaborate further, let’s look at the charts below. In 2022, Infineon (英飞凌) was the market leader for power module in China with a 25% market share. BYD Semiconductor (比亚迪半导体) was the No 2 in China with a market share of 22.9%. In 2023, BYD Semiconductor is now the market leader for power module in China with a market share of 28.9%, while Infineon has dropped to No 2 with a market share of 14.5% (-10.5% YoY). ST Micro and On Semi (安森美) also saw a reduction in their market share.

Source: WeChat

Source: Caixin

As we know by now, BYD Semiconductor can supply 70-90% of BYD’s IGT and SiC requirement. This ratio is the highest among all the global auto OEMs. If BYD gains share in the global automotive market, this is a share loss from the IDMs to the system company (An analogy will be ASIC consumed by hyperscaler vs merchant silicon purchased from Nvidia). The unfortunate news is that BYD is only going to gain market share in the global automotive and EV market.

1. China has the highest EV penetration rate globally and is not showing any sign of slowdown. On the other hand, global EV penetration rate has slowed down with the Trump administration in US and the extension of EU CO2 emission target to 3 years.

2. BYD’s market share in China will increase with the rising penetration rate of EV. BYD has 33% market share in China EV market and only 18% in China Passenger Vehicle market. EV penetration rate will be 60% in China in 2025 and BYD domestic sales is expected to increase by 20-30% this year.

3. If you think that the threat is limited to China sales, BYD is growing its export market rapidly. Export sales took off in 2023 with 334% growth, followed by another 65% growth to 400,000 cars. BYD has guided for export sales to double in 2025 to 800k cars. BYD is doing very well in Asia, Latin America and Oceania due to its affordability.

   

Source: ING

Source: CnEVPost

Beyond BYD who is early to build their internal chip capability, other Chinese OEMs are also catching on to the strategic value of in-house semiconductor. Geely, the 2nd biggest NEV company in China, invested in Zhejiang Geener Microelectronics in 2022. Changan, the 3rd largest NEV company in China, formed a JV Chongqing Anda with StarPower. Great Wall Motor recently took over the full ownership of Wuxi Xindong. Li Auto is also known to be in the process of building an ADAS chipset with the support of Alchip.

Source: Gasgoo

Chinese EV companies are moving in the direction of system companies that control critical parts of the hardware stack from silicon to software. The rise of vertically integrated auto-chip players in China, with BYD Semi as the early incumbent and benchmark, will put pressure on all power IDMs.

Among the global IDMs, we believe that NXP, On Semi and Infineon are most at risk from this rising trend of vertical integration within Chinese automakers. Automotive application is half of their sales for most of the global power IDMs. China revenue is also relatively high in contribution for NXP, On Semi, Infineon and Renesas.

Among the various chip verticals, we believe power discretes are most at risk, followed by MCUs. In contrast, barriers to entry remain higher for PMICs, CIS, infotainment, and ADAS. TI is also becoming vulnerable post the 125% tariff from China.

Another bear thesis for global power semiconductor is the rising overcapacity from Chinese IDMs and Fabless companies. This has led to pricing pressure and market share loss. That will be a topic for another day. While automotive chips might have bottomed cyclically, it will be purely a trade given the structural headwinds they face from the Chinese.

Background

Founded in 2021, SiCarrier is wholly owned by Shenzhen Major Industry Investment Group, which is under the supervision of the Shenzhen State-owned Assets Supervision and Administration Commission (Shenzhen SASAC). Therefore, SiCarrier is a State-owned Enterprise (SOE) under the Shenzhen Government. Its core team includes veteran engineers with more than 20 years of experience from international giants such as ASML and Applied Materials.

Source: SiCarrier

There is market speculation that SiCarrier originated as a semiconductor equipment unit (2012 Starlight Engineering Lab) under Huawei, which was later spun off and acquired by Shenzhen SASAC. It has long been understood that Huawei’s investments in semiconductor equipment are primarily aimed at building a fully domestic, self-sufficient semiconductor equipment supply chain. A key indicator of SiCarrier’s rumored Huawei connection emerged when Li Zhoujian (郦舟剑), Head of Metrology at SiCarrier, appeared in a public interview. Notably, Li Zhoujian also serves as Vice President of Wireless R&D at Huawei and is 1 of 115 representatives for employee shareholders at Huawei. Under the Entity List by BIS, Huawei Starlight Engineering Department is listed as 1 of the aliases of SiCarrier although it is now wholly owned by Shenzhen Major Industry Investment Group.

Source: Huawei

Source: BIS

Core Products

SiCarrier’s debut “Famous Mountain Series” equipment covers the entire semiconductor manufacturing process, including:

• Etching Equipment: The “Wuyi” Etch system supports advanced nodes below 7nm, using a proprietary electrostatic chuck design to significantly boost yield. It has capacitive couple plasma (CCP) system for dielectric etching and inductive couple plasma (ICP) for metal layer etching.

• Diffusion Equipment:

  • “Emei” for Epitaxial

  • “Sanqing” for Rapid Thermal Processor / Annealing

• Deposition Equipment:

  • “Putuo” PVD (benchmarked against AMAT’s Endura)

  • “Changbai” CVD (Chemical Vapor Deposition for 28nm to 5nm)

  • “Ali” ALD (for sub-5nm nodes)

• Metrology & Inspection Equipment:

  • “Yuelu” BFI (Brightfield Patterned Wafer Defect Inspection)

  • “Danxia” DFI (Darkfield Patterned Wafer Defect Inspection)

  • “Penglai” PC (Unpatterned Wafer Surface Defect Inspection)

  • “Mogan” MBI (Mask Blank Defect Inspection)

  • “Tianmen” DBO and IBO (Overlay Measurement)

  • “Yimeng” AFM (Atomic Force Microscopy)

  • “Chibi” XPS (X-Ray Photoelectron Spectroscopy)

• Tester Equipment

  • Chip Probing, Known Good Die and Final Testing

• Photolithography: 28nm immersion lithography system (not directly showcased), with light source wavelength and overlay precision rumored to reach international standards

Source: SCMP

In my view, the more surprising development wasn’t the DUV immersion tool, but rather the progress in ALD, metrology, and inspection equipment. The emphasis on ALD suggests confidence in achieving a sub-5nm breakthrough. ALD plays a critical role in the transition to Gate-All-Around (GAA) architecture and eventually to CFET.

TSMC’s N2 node is reliant on the Gate-All-Around (GAA) architecture which will favor Atomic Layer Deposition (ALD) equipment and etching tool. ASMI is the biggest beneficiary of single-wafer ALD which will continue to grow in importance into CFET and 3D DRAM.

Metrology and inspection equipment has long been a key source of weakness in China’s domestic substitution efforts. These areas encompass a wide range of specialized equipment categories, making SiCarrier’s broad portfolio in this segment particularly noteworthy. Brightfield inspection is more complex than darkfield inspection and commands a significantly higher ASP for KLA. AFM is a niche metrology tool that will increasingly be adopted in the future. The main competition in this area in China is Skyverse which can cover Unpatterned Wafer Defect Inspection, Patterned Wafer Defect Inspection, 3D Surface Profiling Metrology, Film Metrology and Overlay Metrology.

Of course, the actual yield rates and readiness for mass production remain unclear. Another challenge for SiCarrier is the potential concern among Chinese customers about its rumored Huawei background. Huawei has a well-known history of vertical integration and a tendency to compete with its own suppliers and customers. The company is involved with a couple of fabs such as Fujian Jinhua (DRAM), Swaysure (DRAM), Qingdao Si'En (MCU, PMIC) and Shenzhen Pensun (28nm, 40nm foundry).

For Western WFE manufacturers like Applied Materials, Tokyo Electron, Lam Research, and KLA, progress in China’s domestic substitution efforts is inevitable. On the flip side, this shift may actually bring some reassurance to investors, as it reduces dependence on revenue from Chinese customers. SiCarrier will never be a threat to their global business as it is in the Entity List.

Another angle that investors often miss is how fast the China WFE manufacturers are ramping up in capabilities. Because of export control, YMTC has to rely on local manufacturer such as AMEC for etching tool. The top 3 WFE manufacturers in China (Naura, AMEC and ACM Research) have grown their revenue by more than 30% to USD 6 billion. Naura expects local WFE companies to grow their revenue from USD 8.2 billion in 2024 to USD 11 billion in 2025 (11% global market share). The 33% growth is very impressive, considering China WFE will be down 15-20% in 2025. Domestic import substitution rate for WFE will be 35% in 2025.

SiCarrier’s President Speech

SiCarrier’s President Du Liqun made a speech called Challenges and Opportunities in Semiconductor Process Equipment. Surprisingly, the direction that SiCarrier is pursuing is quite similar to what we have seen globally. PPAC remains the key focus of scaling, while 3D scaling is increasingly becoming more important than 2D scaling (Lithography).

• PPAC and shift to 3D architecture:
  Advancements in semiconductors consistently revolve around improving Power, Performance, Area, and Cost (PPAC). Innovations that reduce RC delays and further miniaturize transistors are crucial, with emerging technologies such as advanced lithography, selective deposition, and 3D architectures (like Gate-All-Around, GAA) being key pathways.

• Shift to Atomic-Level Precision:
  With technology nodes progressing from 7nm toward 3nm, equipment precision, particularly in plasma and RF energy control, must improve dramatically by roughly tenfold. Atomic Layer Deposition (ALD) and Atomic Layer Etch (ALE) will increasingly be more important in the future.

• Integration of AI and Simulation Technologies:
  AI and big data present substantial opportunities for optimizing semiconductor equipment operation, predictive maintenance, and process efficiency. SiCarrier emphasizes developing proprietary simulation software and control systems to exploit AI-driven insights fully, thus enhancing equipment performance and reliability.

Full Translated Speech

Source: 芯视点

Ladies and Gentlemen, good morning. First of all, I'd like to express my sincere gratitude to the organizers for providing this wonderful opportunity for us to gather in Shanghai during this vibrant spring season.

Today, it’s raining softly outside. As the proverb goes, "Good rain knows its season, arriving precisely in spring," and similarly, SiCarrier has emerged timely. At SiCarrier Industrial Machinery, our primary business focuses on process equipment and measurement instruments. Over the past few years, we have dedicated ourselves to technical preparations and product development. Today, I am delighted to represent SiCarrier and share some humble insights we've gained through these recent years.

The Fourth Industrial Revolution is approaching, with the AI industry creating significant opportunities for the semiconductor sector. In this context, the critical question is—how much can China's domestic semiconductor equipment industry contribute to the development of our semiconductor sector? What technical strengths can we contribute to promote collective industry progress?

Whether considering memory or logic advancements, PPAC (Power, Performance, Area, and Cost) remains an eternal pursuit we must continually address. Across Logic, DRAM, or NAND, each generation of semiconductor devices consistently improves PPAC performance by 10% to 50%.

Improvements in PPAC illustrate that semiconductor equipment and devices primarily tackle two major issues: First, reducing RC Delay by all possible means; second, further miniaturizing transistor sizes to fit more transistors within a given area. Accordingly, solutions primarily fall into three categories:

Firstly, developing new materials to enhance overall performance. From a dimensional shrinkage perspective, two primary technologies are relevant: advanced lithography techniques for further CD reduction and exploring non-optical technologies due to existing lithography limitations. Technique like SAQP (Self-Aligned Quadruple Patterning) is one such solution recognized across industry.

The industry is also addressing lithography overlay challenges by exploring selective deposition and other techniques. A potential route involves leveraging non-optical techniques, employing our process equipment to partially solve lithographic issues.

Thirdly, there's industry consensus that current 2D architectures no longer suffice, prompting exploration into 3D structures such as Gate-All-Around (GAA) technology for logic and NAND applications.

These pathways—from material innovation to practical engineering application—require joint industry efforts.

Due to CD shrinkage and multiple exposure processes, Atomic Layer Etching (ALE) and Atomic Layer Deposition (ALD) applications will increase significantly. However, using SAQP or similar techniques could increase the total number of process steps by approximately 20%, demanding parallel improvements in yield and process windows for equipment. Expanding these process windows would significantly enhance overall yield.

Moreover, the adoption of 3D structures introduces more complexity, combining selective processes like ALE and ALD, further challenging equipment capabilities.

In terms of new equipment technology, managing three types of energy requires significant enhancements across three dimensions:

First, we require greater precision in energy control, including plasma and thermal energy management.

Second, extensive ALD and ALE usage demands the productivity of equipment to increase exponentially.

Third, expanding the process window remains a perennial goal.

Taking plasma and RF energy management as examples, evolving from 7nm to 3nm technology necessitates a tenfold improvement in energy precision. Hardware circuits' delay synchronization and response speeds similarly must improve tenfold. For instance, we can seek to reduce the response times from 10 milliseconds to 1 millisecond.

Optimizing the process window involves structural adjustments alongside enhanced auxiliary analysis methods. Artificial intelligence driven tuning, big data analytics, and robust computational hardware raise new challenges for hardware and algorithms.

Plasma energy accounts for roughly half of our process equipment. Industry viewpoints typically split between simulation and experimental approaches, which have coexisted competitively for many years.

In the recent 2 years, leading firms have been acquired by major international and domestic corporations. This phenomenon underscores that plasma management inherently integrates forward design, simulation, and diagnostics. Profoundly understanding the first principles of chamber operations is essential for guiding precise future designs, motivating SiCarrier to develop plasma simulation software several years ago.

Our simulation capability spans from atomic physical models and chamber chemistry to reaction models and diagnostics. Our simulation software, "Wen Yuan," benchmarks against the industry’s highest accuracy standards. "Wen Yuan" is inspired by the poetry line, "Ask the stream why it's so clear, for it is fed by flowing waters."

While we've completed our simulation strategy, converting designs into reality remains challenging. Synchronizing RF sources, matchers, chucks, coil magnetrons, gas valves, and detectors with our equipment necessitates comprehensive integration, a path SiCarrier has thoroughly addressed from system design to hardware, components, and algorithms.

Regarding hardware responsiveness, shifting from traditional CVD/ETCH to ALD/ALE significantly raises demands on transient response and stabilization times.

How can equipment consistently deliver excellent ALD characteristics? Equipment control systems play a critical role. While PLC systems dominated previously, we increasingly see advanced processors and logical systems adoption. Achieving fast, accurate, and stable hardware performance remains a future imperative.

Recognizing this, SiCarrier has developed an entirely self-designed control system, substantially improving control capabilities compared to traditional PLC systems.

Looking ahead, expanding process windows remains challenging. Leveraging AI, from semiconductor equipment physics and design data to fab-wide operational and power consumption data, presents vast opportunities. Despite myriad parameters and process variables, full utilization remains untapped. Integrating big data with physical simulation models could drive intelligent optimization and predictive maintenance.

SiCarrier has strategically positioned itself for future AI-driven optimization and smart maintenance. We've achieved promising accuracy in lifecycle prediction for specific components—within ten days—based on their physical characteristics and process impacts, aiming for larger-scale models providing optimal client solutions.

Our overall design philosophy emphasizes synchronized advancement across processes, materials, and equipment. Through precision energy control, intelligent process window tuning, and rapid, stable, and precise control systems, we aim to accelerate technological and material evolution, facilitating finer process management.

Guided by this vision, SiCarrier has developed six categories of processing and inspection equipment, addressing diverse logic and memory scenarios while supporting future advancements.

Exploring semiconductor physics boundaries remains our relentless pursuit, representing an infinite horizon as semiconductor people. SiCarrier remains committed to our technological roots, hoping to collaborate innovatively with partners for mutual success, providing customers with novel choices.

Semiconductor world, new choices, SiCarrier. Thank you.

Deposition - Stable share in a growing market

Deposition equipment involves tool that deposits thin films on the wafer – including thermal oxidation furnaces, Chemical Vapor Deposition (CVD) reactors, Physical Vapor Deposition (PVD) sputtering tools, and Atomic Layer Deposition (ALD) systems.

TEL has a comprehensive offering in deposition, historically rooted in batch oxidation / diffusion furnaces and CVD. According to TEL, its global market share in 2023 for overall deposition systems was 31% with major competitors including Applied Material, Kokusai and ASM International. TEL classifies its deposition into three types: Oxidation / Diffusion, CVD, and ALD. TEL held ~40% global share in oxidation / diffusion equipment, 40% in CVD, and 16% in ALD. For clarity, ALD refers to semi-batch or single wafer ALD, while oxidation / diffusion furnace is batch ALD.

Source: Tokyo Electron

Starting with oxidation / diffusion furnaces, TEL’s main competitor is Kokusai in Japan. Kokusai has a dominant position in batch ALD for 3D NAND. As aspect ratio goes up with the layer race in NAND, there will be higher demand for batch ALD due to its higher productivity. As NAND producers work towards 300-400 layers, higher deposition will drive TAM growth which will benefit TEL’s revenue growth in deposition.

Source: Kokusai

Similarly in single-wafer ALD, Tokyo Electron faced a strong competitor in ASM International. ASM International is the dominant single-wafer ALD provider for advanced logic application with TSMC. With the adoption of Gate-All-Around (GAA) by TSMC at N2, ASM International will be a key beneficiary. TEL semi-batch ALD tool will find it tough to gain share in this space. TEL faced very strong competition from Kokusai and ASM International who are very focused on their core business of ALD.

Triase is the key CVD product within Tokyo Electron’s deposition portfolio that has a high market share of 40%. The single-wafer CVD core focus lies in metal film deposition, particularly for Titanium Nitride (TiN) in DRAM electrode formation. Its Advanced Sequential Flow Deposition (ASFD) technology can deliver highly conformal, precisely controlled thin films through the use of sequential gas pulses with faster deposition rates than ALD. Operating at lower temperatures, it is also more suitable well-suited for temperature sensitive processes.

Triase, Source: Tokyo Electron

Tokyo Electron has introduced a new Episode 1 CVD equipment which has 45% smaller footprint than Triase. In addition, this new platform is able to integrate 8 process modules, which is twice that of Triase.

Source: Tokyo Electron

Etching - Gaining share in NAND conductor etching

Etching is a process that selectively removes material from a wafer's surface to create structures and patterns. Tokyo Electron is strong in dielectric etch with more than 50% share​, whereas Lam Research leads in conductive etch (metals, polysilicon)​.

Etching is a particularly important process in 3D NAND as producers seek to increase the layer count. Scaling is done vertically by stacking memory cells vertically in a 3D architecture instead of shrinking transistor area through lithography. The challenge lies in the high aspect ratio (HAR) etching as the layer count increases at the trendline of 30% every 1.5 years. Aspect ratio is the height to width ratio when etching deep and narrow channel holes. Aspect ratio as high as 100:1 can lead to difficulties in achieving uniform etching. Tool productivity can also be another problem as doubling the layer count leads to doubling of the time taken for etching.

Source: Tokyo Electron

Recognizing the challenges posed by increasing HAR, TEL embarked on developing a novel etching technology in 2014. In 2023, TEL announced the new TELAVES cryogenic etcher. Notably, it achieves etch depths greater than 10 µm at rates 2.5 times faster than previous methods, while also reducing power consumption by over 40%. This is through the combination of High-Efficiency Rectangular Bias (HER) and Phosphorus + Hydrogen based Fast Ion Etch (PHastIE) technology.

​Tokyo Electron's HER technology utilizes rectangular radio frequency (RF) wave to maintain a vertical ion incidence angle during the etching processes. Ion incident angle is varied in the conventional sine wave technology which results in bowing problem.

Source: Tokyo Electron

The PHastIE process leverages innovative chemistry and cryogenic temperatures to enhance high-aspect-ratio etching performance. By employing a novel process gas Hydrogen Fluoride (HF), deposition at feature openings is minimized, while the cryogenic environment effectively protects sidewalls during etching. This approach reduces bowing and increases etch rates.

There are 4 key etching processes for 3D NAND

1. Channel Hole: Deep holes etched to form the transistors

2. Slis: Etched regions that isolate word lines, ensuring proper electrical functionality.​

3. Multi-level Contact: Holes etched to establish connections between different metallic wiring layers.​

4. Staircase: Connection for access to wordline in each layer

Today, TEL has high share in multi-level contact and word line isolation. Lam has almost 100% share for the extremely high aspect ratio channel hole etch in 3D NAND​. TEL’s new cryogenic etcher breaks that monopoly, offering better throughput for 3D NAND of more than 400 layers. Samsung Electronics will be TEL 1st NAND customer using their cryogenic etcher for 400L 3D NAND. SK Hynix is also currently testing TEL’s cryogenic etcher.

For perspective, TEL projects that the conductor etch market for NAND is worth $2 billion in 2027. Assuming a 50% market share, this is an $1 billion incremental revenue for TEL. Lam Research is not sitting still as it has launched Cryo 3.0 in response. However, Lam Research is late to the cryogenic etcher game by 1.5 years and customers are incentivized to introduce a 2nd supplier to break the virtual monopoly. Kioxia is expected to be Lam Research’s Cryo 3.0 customer.

Bonder / Debonder - Exciting new opportunity

Wafer bonding equipment is used to fuse two wafers together – either permanently (for 3D stacking) or temporarily (for handling thinned wafers). Debonders remove temporary bonding materials so the wafer can be processed and later separated. This is a small but rapidly growing segment parked under the Prober segment for revenue.

Lets start with permanent wafer bonding equipment which is also known as wafer-to-wafer (W2W) hybrid bonder. In W2W hybrid bonding, two fully processed wafers are precisely aligned and bonded together, establishing direct connections between their corresponding interconnects. This is currently in use for the production of CMOS image sensor. This is different from chip-to-wafer (C2W) hybrid bonding where individual dies are connected onto a target wafer without the use of traditional solder-based interconnects. Currently, BESI is the market leader for C2W hybrid bonder while EV Group is the market leader for W2W hybrid bonder.

Source: Tokyo Electron

W2W hybrid bonder is expected to experience strong growth this decade due to innovation happening in logic and NAND roadmap. Backside Power Delivery (BPD) will be adopted by Intel in 2025 and by TSMC for A16 in 2026. Traditional power delivery networks route power and signals through the front side of the wafer, leading to congestion and increased resistance as device scaling continues. BPD addresses this by relocating the power distribution network to the wafer's backside, thereby decoupling power and signal interconnects. W2W hybrid bonding is used to bond the front side of the 1st wafer to the carrier wafer for further processing.

Source: Applied Materials Masterclass on BPD

W2W hybrid bonding also enables the direct bonding of 2 wafers, placing the peripheral circuit under the memory cells for 3D NAND. This is similar to the innovative Xtacking technology adopted by YMTC that allows them to catch up to the competition. Through this peri under cell (PUC) technique, the chip size is reduced and the number of stacked layers can go up. Kioxia has adopted PUC in its Gen 8 BiCS technology and SK Hynix has sampled at 321L NAND.

Source: SK Hynix

Source: Kioxia

Beyond CIS, BPD and PUC, W2W hybrid bonding will be adopted for 3D DRAM in memory and CFET in logic. Tokyo Electron expects the market TAM for bonder to increase from JPY 100bn in 2025 to JPY 300 billion (USD 2 billion) in 2030. Currently, TEL has a 20% market share for W2W bonder with its Synapse Si bonder. If they can secure a market share of 20-40% in the bonder market, the revenue potential will be USD 400-800mn in 2030.

Source: Tokyo Electron

For the backend equipment, Tokyo Electron is the market leader for temporary bonder debonder. The biggest usage of temporary bonder debonder is currently for the HBM market. In order to stack multiple dies while maintaining the aspect ratio of through silicon vias (TSV), wafer thinning has to be carried out. The memory wafer has to be temporarily bonded onto a carrier wafer before it is thinned. To meet the 775um requirement for the HBM3e 12-Hi used in GB300, each individual chip has to be as thin as 32 um. After thinning is done, the wafer is then debonded and diced into individual dies. Tokyo Electron is the main supplier of temporary bonder debonder for SK Hynix, while German competitor SUSS Microtec supplies Micron and Samsung.

Source: SK Hynix

Cleaning - Relatively stagnant

This is not an exciting segment given limited content growth and market share gain opportunity. As seen from the chart from Screen, the market leader in cleaning, there is a limited increase in number of cleaning step for N2 (GAA + BPD). While TEL may gain some market share from Screen, it is at risk of losing low to mid end market share to Chinese competitors such as ACM Research.

Source: Screen Holding

Acrevia - Pattern shaping tool

Launched in July 2024, ​Tokyo Electron's Acrevia is a system designed to refine patterns produced by EUV lithography. It utilizes directional gas cluster beams to precisely etch feature sidewalls, enabling critical dimension adjustments and enhancing pattern fidelity. TEL has also incorporated its cleaning expertise into Acrevia with low damage cleaning capability. This is similar to Centura Sculpta, the pattern shaping tool launched by Applied Materials. Given that a low-NA EUV machine from ASML can cost close to EUR 200 million, Acrevia is a cost effective solution that can potentially reduce the need for EUV multi-patterning. Samsung Electronics had started testing Acrevia for their foundry business.

Risks

1. High Revenue Exposure to China

China came to the rescue of major WFE suppliers during the 2023 downcycle. In 2024, China was 40% of TEL sales which had 3 potential issues

• US or Japan government may impose further restriction on export of WFE equipment to China

• Some of the demand in 2024 was pull-in demand as Chinese foundries do not know if the export control will be further tightened

• Chinese WFE manufacturers (AMEC, Naura, ACM Research) are gaining share of domestic WFE from the foreign manufacturers

TEL expects China sales to decline by 20% to account for 30% of sales in 2025. While this is still higher than what investors are comfortable with, we should expect China contribution to further decline into 2026.

2. Appreciation of Japanese Yen

For those who enjoy a nice holiday to Japan, you will have noticed that the Japanese Yen (JPY) had depreciated by close to 40% since 2022. This has helped to inflate the JPY sales and margin of many SPE companies in Japan who receive USD for international sales. With core inflation of Japan creeping up and affecting the cost of living for the local Japanese, pressure is on the Bank of Japan (BOJ) to hike rate. Either rate hike from BOJ or rate cut from US Fed will send the JPY appreciating again. This will be a double whammy for many Japanese exporters.

However, Tokyo Electron has been selling its products denominated in JPY and has not benefitted from the sharp depreciation of JPY. The only tangible benefit for TEL is that their product pricing is now more competitive against the foreigner. This will not boost sales immediately as process of record (POR) is often decided years before. TEL has started to increase the JPY denominated pricing of its product and will not be negatively impacted by an appreciation of JPY as their local peers. In fact, TEL had reported lower market share because the SPE market is denominated in USD.

Conclusion

Over the next 5 years, Tokyo Electron is well positioned to be a share gainer in the SPE market especially with its cryogenic etcher and W2W hybrid bonder. Demand growth for etching, bonder / debonder are also expected to be faster than the overall SPE market. China remains a significant part of revenue and investors will be glad to see lower contribution from China going forward.

This concludes the first deep dive done by Nomad Semi. If you like the content, do subscribe to make sure you receive the latest post.

Tokyo Electron (TEL) is the 4th largest global supplier of semiconductor production equipment (SPE). It has a broad SPE portfolio similar to Applied Material, while peers like ASML, KLA and Lam Research are more specialized. The most dominant product in TEL’s portfolio is photoresist coater / developer system where they have a 90% market share. Throughout its history, TEL evolved through multiple phases – from importer to co-manufacturer, then to an independent equipment developer.

History

Tokyo Electron was founded in 1963 by Norio Kubo, a former Nissho Iwai trading company employee, with startup capital provided by Tokyo Broadcasting System (TBS). Initially, TEL operated as a distributor of imported electronic equipment – exporting car radios and importing semiconductor fabrication tools. Early on, TEL forged partnerships with U.S. manufacturers like Thermco (diffusion furnaces) and Fairchild Semiconductor, developing deep technical expertise in the operation of SPE.

In 1968, TEL transitioned into manufacturing SPE by forming a joint venture with Thermco to produce diffusion furnaces in Japan​. TEL decided to withdraw from the export operation in 1974 due to strong yen post 1971 Nixon shock and 1973 oil shock. Subsequently, it formed joint venture with Lam Research to produce etching equipment and Varian Semiconductor (acquired by Applied Materials) to produce CVD and PVD equipment.

The next evolution came during the late 1980s semiconductor downcycle. As both Lam Research and Thermco were hit hard, they requested TEL to acquire their shares in TEL Lam and TEL-Thermco. TEL became a SPE company and was supported by customers such as Toshiba, NEC and Hitachi. This was at a time when Japanese manufacturers dominated the memory market with their higher yield rate and lower cost. From 1989 to 1991, TEL was the world’s biggest SPE producer. The Plaza Accord and the 1986 US-Japan Semiconductor Trade Agreement set the stage for the American semiconductor manufacturers to regain share in the 1990s (Intel also open a new market in microprocessor).

Source: Chips and Change

With the decline in the local semiconductor market, TEL started to develop a global footprint by cooperating with partners such as Varian in Europe, KLA in US and Hermes-Epitek in Taiwan. In 1994, the decision was made to switch to a direct sales model in its overseas market.

One final key development was the announced merger with Applied Materials in 2013. With the consolidation of memory and logic producers, Applied Materials wanted to consolidate to improve its bargaining power against the customers. While the merger was called off in 2015 due to anti-trust concerns, Tokyo Electron’s then CEO Tetsuro Higashi was inspired by Applied Materials focus on shareholder returns. A share repurchase plan of JPY 120 billion was announced in 2015 which reduced the total outstanding shares by 8% in year. 3 more share repurchase plans were announced in 2020, 2023 and 2024. Share repurchase is now an important source of shareholder returns for all major SPE companies today.

Source: Tokyo Electron

Revenue overview

The company's product portfolio spans multiple key process steps in semiconductor production, including deposition (CVD, ALD, oxidation/diffusion furnaces), etching (dielectric and conductive plasma etch, including its latest cryogenic etch for 3D NAND), and cleaning (single-wafer and batch wet cleaning). TEL is also the undisputed leader in coater / developer systems, with a 90% global market share, making its track equipment integral to EUV and DUV lithography. It has also expanded into wafer bonding and debonding systems to address the growing demand for heterogeneous integration and advanced packaging.

Source: Tokyo Electron

By revenue, the 4 key products (coater / developer, etch, deposition and cleaning) account for 95% of its product sales. Key clients such as TSMC, Intel and Samsung account for 50% of their sales.

Field Solutions business, which contributes approximately 23% of total revenue, serves as a recurring revenue stream, providing a stabilizing counterbalance to the cyclical nature of new equipment sales. This segment encompasses servicing, spare parts, upgrades, and used equipment refurbishments, ensuring that TEL’s vast installed base of over 96,000 tools remains operational at peak efficiency throughout their lifecycle. Field Solutions sales have grown at a CAGR of 14% in the last 10 years.

Source: Tokyo Electron

Competitive Landscape

The SPE industry is dominated by a handful of large players, each with areas of specialization. Tokyo Electron is ranked #4 globally by revenue, alongside Applied Materials, ASML, and Lam Research. The SPE industry is highly consolidated with the top 5 companies accounting for 75% of the industry sales. ASML is the monopoly supplier of EUV lithography system and is a key partner of TEL. Lam Research is a dominant supplier of etching equipment and will be the most direct competitor to TEL over the next few years.

According to TEL’s estimates, it ranked No.1 worldwide in Coater/Developer tracks, Gas Chemical Etch systems, Diffusion furnaces, and Batch Deposition systems, and No.2 in Cleaning systems, Plasma Etch systems, Metal deposition, and Wafer Probers. This impressive breadth across critical process steps makes TEL a primary supplier to any leading-edge fab.

Source: Tokyo Electron

With peak lithography over the next 5 years, non-lithography SPE makers will benefit as deposition and etching gain share.

Now, we will examine their market share trajectory in the key products.

Coater / Developer - Tokyo Electron will defend its share against Lam Research’s Dry Resist

Coater / developer systems are used in the lithography process to coat wafers with photoresist before exposure and to develop the latent image after exposure. TEL is the undisputed world leader in this category with the CLEAN TRACK coater / developer systems (models like ACT, LITHIUS Pro).

TEL holds 90% share of the coater / developer market​ and 100% share of the EUV lithography coater / developer market. TEL’s tools are tightly integrated with ASML scanners and their close partnership is a barrier of entry for new competitor. Key photoresist suppliers are also all Japanese firms (Shin-Etsu, JSR and TOK) which have close cooperation with Tokyo Electron.

Source: ASML

This segment has been a steady cash cow for TEL, but it’s also at the forefront of a technical challenge due to emerging Dry Resist technology from Lam Research. CAR (Chemically Amplified Resist) is the conventional photoresist used in today’s lithography. It’s a liquid resist spun onto wafers by TEL’s coater. CAR has served well but is facing issues like stochastics and resolution limits as the industry migrates to 2nm and beyond.

Lam Research unveiled a dry resist technology for EUV – essentially an ALD (atomic layer deposition)-based vapor-phase deposition process that deposits a resist film , rather than spin-coating. This dry resist can be extremely thin and achieve high resolution, potentially enabling 2nm patterning. Dry resist, being vapor-deposited, does not rely on liquid processing, thereby eliminating surface tension-driven pattern collapse. If dry resist were widely adopted, the lithography process flow might change – instead of a TEL coater applying resist, Lam’s tool would deposit it. That could disrupt TEL’s near monopoly in resist coating for the critical layers.

Source: Lam Research Investor Day 2020

Despite the threat from Lam Research, they have yet to achieve the $1.5 billion revenue over 5 years target that they set in the 2020 Investor Day. In the 2025 Investor Day, Lam Research has the same target of $1.5 billion over the next 5 years. After 5 years, dry resist adoption is still slow as Lam Research has only announced 1 memory client. Dry resist requires new deposition and etching equipment which are much more expensive. The throughput is also lower as the cycle time may be longer compared to the high-throughput spin-coating process used for CAR.

Source: Lam Research Investor Day 2020

Source: Lam Research Investor Day 2025

TEL is also not sitting still as they are developing the next generation wet resist process called MOR (Metal Oxide Resist). This is a newer inorganic resist pioneered by Inpria which had been acquired by JSR. MOR advantage is that it can achieve similar pattern integrity benefits while still being compatible with existing wet development processes, allowing fabs to avoid the extra cost of implementing plasma-based dry resist deposition tools. MOR process is able to prevent pattern collapse for resist pattern of 8nm which is similar to the dry resist process.

Source: Tokyo Electron Investor Day 2025

Given the 1/3 cost advantage over dry resist, MOR is expected to be introduced at 10A for logic and 1b nm for DRAM. This will effectively stop the share gain opportunity for Lam Research. SK Hynix is reported to have adopted MOR solution for 1c nm DRAM and Samsung is testing it too. TEL is also working with ASML on the coater / developer system for High-NA EUV at 10A.

Source: Tokyo Electron Investor Day 2025

Part 2 of the deep dive will look into deposition, cleaning, etching and bonder. It will explore some of the key growth opportunities for Tokyo Electron in etching and bonder.

Part 2 has been published:

In memory, we are starting to see uptick in DDR5 prices while Trendforce is seeing NADN price inflection in 2H. China’s 3C stimulus (15% of smartphone ASP, capped at RMB 500) had led to a demand uptick in both PC and smartphone. In the 1st week of the government subsidies (Jan 20), smartphone sales in China grew by 60% yoy or more than 30% if adjusted for CNY. This led to a drawdown in memory inventory, reducing the temporary oversupply situation. NAND price is inflecting in 2H as multiple producers (Samsung, Micron, Hynix) have started to cut NAND production.

Source: Trendforce

Memory demand is likely to further accelerate into 2H 2025. iPhone 17, which will be launched in Q3 2025, will feature an upgrade in DRAM memory content from 8GB to 12GB. According to TP Huang, most of the major smartphone OEMs will incorporate DeepSeek into smartphone. Running DeepSeek model could drive replacement demand and higher DRAM content for the inference.

TP’s Substack

The massive DeepSeek affect

I first posted about DeepSeek in December of 2023, but did not make a note of them. They were unknown to me until probably Q3 of 2024 when v2 already came out. At the time, there was already a lot of rumbling from some people in Silicon Valley about how good DeepSeek was due to the fantastic research. And then when V3 came out in December, it made a lot…

Read more

a year ago · 26 likes · 1 comment · TP Huang

China is all-in on AI
Despite the initial fear of DeepSeek on GPU demand, we have seen massive Jevons Paradox in play in China. The adoption of DeepSeek R1 throughout China is driving inference demand through the roof. Taiwan’s supply chain first heard the news of the increase in Hoppers orders right after CNY is over. In the middle of January, Hopper forecast was slashed by 80-90%. Last week, Hopper forecast has doubled from the January lows and this is certainly not the end.

Tencent had ordered 200k H20 GPUs and a lot more is needed to serve R1 to more than 1.3 billion users on WeChat. On the 1st day of beta testing on WeChat, there was insufficient server capacity and Tencent had to subsequently redirect traffic to their chatbot YuanBao. Tencent will report results next month, so we will know the magnitude of increase in capex.

独家｜微信AI搜索调用量超载 搜索需求跳转至聊天机器人“元宝”

In the latest earnings, Alibaba said that the pursuit of AGI is their primary objective and that the investment over the next 3 years will be more than what they have invested in capex the last 10 years. This will work out to be at least USD 14 billion in capex this year and possibly even much higher in 2026. It is possible for Alibaba to spend as much as USD 25 billion in capex in 2026. Bytedance might also raise their capex to RMB 200 billion from the initial expectation of RMB 160 billion.

There will also be more capex from China Mobile, China Telecom and China Unicom. China SASAC (State-owned Assets Supervision and Administration Commission of the State Council) has issued a call for Central SOEs to study and implement the spirit of President Xi’s speech on developing AI. This is China all-in on AI, a national movement that is bigger than any sovereign AI effort we have seen.

In short, DeepSeek for China is the equivalent of ChatGPT moment in the USA. The massive increase in data center spendings the last 2 years by the FAMG will now be replicated in China. The difference this time is that the demand in China will be primarily driven by inference rather than training. Inference demand represents monetization opportunity and we will not doubt the capabilities of Chinese to integrate them in applications. Nvidia’s H20, RTX 5090 and RTX 4090 are highly sought after now. This demand will continue for as long as US government does not ban the chips.

At the same time, there will be a proliferation of domestic AI chips made by Chinese companies such as Huawei, Cambricon, Alibaba’s T-Head, Meta-X, Biren and e.t.c. Most of these will be manufactured at SMIC, whose capacity will now be the bottleneck for Chinese effort at domestic substitution for AI chipset.

Many listed Chinese companies will be a big beneficiary similar to their US and Taiwanese counterparts the last few years. Here is a list of companies in the Chinese supply chain:

• Foundry: SMIC (981 HK)

• Data Center: GDS, 21Vianet

• GPU: Cambricon (688256 CN), Hygon (688041 CN)

• Liquid Cooling: Shenzhen Envicool (002837 CN)

• Networking Switch: Ruijie Network (301165 CN)

• AI Chip Testing: Shanghai V-Test Semiconductor (688372 CN)

• Optical Transceivers: Huagong Tech (000988 CN)

• Server ODM: Inspur (000977 CN), Dawning Information (603019 CN)

• Power Supply: Megmeet (002851 CN)

Source: Tokyo Electron, Lam Research, KLA, Kokusai

The WFE companies are not expecting a big increase in overall WFE spend in 2025. While Lam Research and KLA are looking at mid single digit growth in WFE, Tokyo Electron and Kokusai are looking at a flattish year. This is still slightly better than the expectation of a decline in WFE in 2025 due to weak memory outlook and capex cut at Samsung, Intel.

NAND > TSMC > DRAM > Logic

Source: Tokyo Electron, Lam Research, KLA, Kokusai

Contrary to what some might expect, NAND is actually the strongest growth driver for WFE in 2025. Tokyo Electron expects NAND capex to double while Kokusai is seeing a 25% increase. Both Lam Research and KLA are also seeing growth in NAND capex. On the other hand, outlook for both logic and DRAM are flattish.

In NAND, the industry is looking to transition the current installed capacity to higher layer counts to achieve better device performance at lower bit cost.

But at the same time, on the last call, I mentioned this point that about 2/3 of the bids are still being manufactured on nodes below 200 layers. And what happens as you move above 200 layers is not only do you have to upgrade the existing tools, but you have to start adding additional tools to deal with the complexity of that transition.

Source: Lam Research

NAND prices continue to decline and major producers are cutting production level, so no one is really expanding greenfield capacity. As NAND spending has been at a very subdued level for 2 years (down 50% from 2022 peak), memory makers are starting to upgrade their layer count again. We are definitely not in the new era of NAND that Western Digital was talking about where there is an end to the layer race.

Source: Western Digital - The New Era of NAND

Among the major NAND producers, it is likely to be Samsung, Hynix and YMTC that are driving the upgrade cycle. Samsung is upgrading its V6 NAND to V8 this year and will be developing 400L NAND in 2026. Hynix will be upgrading to 321L NAND this year, followed by 400L NAND in 2026. YMTC is working hard to achieve a breakthrough to 160L NAND with the help of AMEC in China. Lam Research is no longer able to supply etching tool to YMTC. While Kioxia will like to spend more, they are constrained financially and by their partner Western Digital.

Logic - TSMC is the kingmaker

Leading edge logic demand is strong as TSMC is looking at mid-20% growth in revenue for 2025. TSMC had guided for mid 30% in capital intensity last year so it was no surprise that it raised its capex from $ 29.8 billion in 2024 to $38 - 42 billion in 2025. With a 20% revenue CAGR from 2024 to 2029, TSMC will continue to spend more in capex on the leading edge. N2 is set to start mass production this year and ramp in volume in 2026. As the number of new tape-out for N2 in the first 2 years will be higher than both N3 and N5, N2 is a big volume ramp in 2026 and 2027. N2 is TSMC’s 1st GAA node, so this will disproportionately benefit ASMI and Lam Research which are the main ALD provider.

Most will have known that Samsung and Intel have cut their logic capex. Intel has further cut their gross capex in 2025 from $20-23 billion to $20 billion. This is a 20% capex cut in 2025 after a 20% capex cut in 2024. Intel Foundry is not getting any significant customer in the next 2 years. Nova Lake, which is the next generation client CPU after Panther Lake, will continue to have some tiles outsourced to TSMC. Granite Rapid has been delayed to 1H 2026, while Falcon Shore will no longer be sold externally.

For Samsung, next generation Galaxy S25 will be 100% Qualcomm chipset as they are not using their in-house Exynos. This is the 2nd time in recent year since S23 that Exynos is not used in Samsung’s flagship phones. As Samsung’s lead edge node is progressing far worse than Intel, it has been losing clients such as Qualcomm to TSMC. TSMC has effectively monopolised N3 and beyond node. I highly doubt Samsung can turnaround the foundry business unless it gave up on the leading edge. The big question for Samsung Foundry is what are they going to do with the Taylor fab. Equipment move-in for Taylor fab has been paused and the ramp has been delayed from 2024 to 2026. Because N4 yield is unsatisfactory, Samsung is betting instead on N2 ramp in 2026 to save them. Samsung had earlier announced that Taylor fab investment is $17 billion and total spending in Texas will run up to $40 billion. Chips Act grant was subsequently cut to $4.75 billion from $6.4 billion. Samsung is not going to get any large order for N2, so this could become a $17-40 billion asset that has to be written off eventually.

DRAM

DRAM price continues to decline with the ramp of CXMT output, while HBM demand remains very strong. With DDR4 oversupply, DRAM producers are shifting their product mix to DDR5 and HBM. Although DRAM price is expected to recover in 2H 2025, overall DRAM capex will be muted. Both Hynix and Micron are constrained in their ability to expand capacity meaningfully due to a lack of cleanroom space. Hynix has guided for limited incremental capex with the mix shifting more towards infrastructure for Yong-in fab in 2027. Hynix’s M15X equipment spend will be about $10 billion spread over 2025 and 2026. Micron is waiting for Idaho and New York fab to be ready in 20-27 and 2028. Samsung is guiding for flattish capex in 2025 with a reduction in foundry and increase in memory (more for NAND).

China

China was a hot topic for WFE manufacturers as it accounts for 40% of their revenue in 2024. With the export control and pull-forward demand (especially DUV) from China, it was inevitable that China revenue will decline. China is now going to be 30% of revenue for the WFE producers and likely be even lower in 2026. ASML’s China sales is a leading indicator for the other WFE’s China sales. Both KLA and Lam have seen a $500 million and $700 million impact from export control respectively.

Another angle that investors often miss is how fast the China WFE manufacturers are ramping up in capabilities. Because of export control, YMTC has to rely on local manufacturer such as AMEC for etching tool. The top 3 WFE manufacturers in China (Naura, AMEC and ACM Research) have grown their revenue by more than 30% to USD 6 billion. Naura expects local WFE companies to grow their revenue from USD 8.2 billion in 2024 to USD 11 billion in 2025 (11% global market share). The 33% growth is very impressive, considering China WFE will be down 15-20% in 2025. Domestic import substitution rate for WFE will be 35% in 2025.

China WFE demand is expected to decline as CXMT is slowing down their capex in 2025 while mature logic is suffering from overcapacity. On the other hand, YMTC is expected to ramp up its 160L investment after being crippled temporarily by the export control.

Share Shift

Tokyo Electron has secured mass production POR for NAND channel hole etching with its cryogenic etching for 2026. Given Tokyo Electron’s market share of 10-15% in 3D NAND etching, this will be a market share gain opportunity from Lam Research. However, I do not expect Tokyo Electron to monopolise cryogenic etching as Lam Research has come out with similar product.

Lam Research has secured POR for dry resist for DRAM, which will take away some market share from Tokyo Electron.

ASML - Peak lithography until High-NA arrives in 2030

The bigger share shift opportunity remains the shift towards materials engineering from lithography scaling for the rest of the decade. Deposition and etching will outperform as lithography intensity is reduced. Logic metal pitch will only shrink by 10% from 23nm in 2023 to 21nm in 2027 compared to the 20% shrink from 28nm in 2020 to 23nm in 2023. TSMC’s N2 node is reliant on the Gate-All-Around (GAA) architecture which will favor Atomic Layer Deposition (ALD) equipment and etching tool. ASMI is the biggest beneficiary of single-wafer ALD which will continue to grow in important into CFET and 3D DRAM. Lam Research is seeing its ALD revenue growing by at least 50% in 2025 from $1 billion in 2024. Lam Research will only benefit from the use of lateral etching in GAA.

Source: ASML Investor Day

Source: Lam Research

As TSMC moves towards A16 in 2026, backside power delivery will be the key driver. EV Group will be a big beneficiary as the main provider of wafer-to-wafer hybrid bonder. CMP tool (Applied Material and Ebara) and grinding tool (Disco) will also benefit from content growth.

ASML will outperform WFE again when High-NA EUV is adopted by TSMC near the end of the decade. 5 years is a long time and it remains to be seen if there will be further delay in adoption. 3D DRAM is also a threat to ASML in the longer term, although ASML don’t see it happening in 2030.

Conclusion

With China de-risked and the underperformance against SOXX, it might be time to relook at the WFE manufacturers again. Companies such as ASMI, Lam Research and KLA are clear WFE share gainers over the next few years. Tokyo Electron and Applied Material will benefit to a smaller extent, while ASML’s sales underperformance will be seen from 2026. China sales will continue to dwindle for foreign players as domestic substitution continues.

2026 should be a stronger year in capex spending as TSMC continues to increase capex to meet the demand of N2. Hynix and Micron will also start to pull in equipment in 2H 2026 for their new greenfield plants.

1. Revenue guidance for 2025 is now EUR 30-35 billion as compared to 30-40 billion earlier

2. Low NA EUV shipment will now be <50 units in 2025 as compared to expectation of 65-70

3. Gross margin of 51-53% in 2025 as compared to 54-56% earlier

4. Net booking of only EUR 2.6 billion (EUV was EUR 1.4bn or 7 units) as compared to expectation of more than EUR 5 billion

A shipment reduction of more than 20 EUV units is shocking for an equipment with lead time of more than a year. In addition, memory customers are increasing their adoption of EUV layers.

It is not China

The sharp decline of China business was what first came to mind. ASML expected China to go back to a more normalised percentage of sales (20%) as it had been in the backlog. China had been more than 40% of sales in the last few quarters, so this implies a decline of 30% yoy in 2025.

China had been one of the key risks for semicap companies given the high contribution to many semicap companies in the downcycle. We can’t expect China to continuously expand capacities at all costs. There are signs that SMIC, Hua Hong and YMTC are no longer expanding capacities as aggressively as they were before. In addition, there had been quite a bit of demand pull-in for fear of further export restriction by the US government.

However, guidance on DUV was not affected much due to the sharp rise in DUV orders from non-China customers.

Samsung and Intel are the culprits

From the press release, it certainly seems that both Samsung and Intel are having much slower capacity ramp as a result of their inferior technology and hence lack of customer.

"While there continue to be strong developments and upside potential in AI, other market segments are taking longer to recover. It now appears the recovery is more gradual than previously expected. This is expected to continue in 2025, which is leading to customer cautiousness.

Regarding Logic, the competitive foundry dynamics have resulted in a slower ramp of new nodes at certain customers, leading to several fab push outs and resulting changes in litho demand timing, in particular EUV. In Memory, we see limited capacity additions, with the focus still on technology transitions supporting the HBM and DDR5 AI-related demand.

This is nothing too surprising for those who have followed the 2 IDMs. 2 months ago, Intel announced that they will reduce gross capex by more than 20% to $25-27 billion in 2024 and $20-23 billion in 2025. Intel had delayed the construction of 2 fabs in Ohio and 2 fabs in Germany by more than 2 years.

Samsung had delayed its Taylor fab from 2024 to 2026 due to poor yield. Samsung’s execution on advanced nodes has lagged even that of Intel. For Samsung’s Galaxy 25, Snapdragon 8 Gen 4 will be adopted instead of the internal Exynos chip. Snapdragon 8 Gen 4 is fabbed at TSMC N3 instead of Samsung. Without a significant internal or external customer, it is no surprise that Samsung has cut its foundry capex massively.

Didier Scemama Excellent. And a follow-up to that would be, how much of the pushout is a reflection of just the end demand being pulled versus maybe several of your customers struggling with process technology and attracting effectively customers to justify the construction of those factories?

Christophe Fouquet Chief Executive Officer I think it's both. So it's a mix of that. I think that we learned the slower recovery first, because I think this affects every single customer. So we are still quite optimistic about AI. I think today without AI, the market would be very sad, if you ask me. But for the rest, I think our customer continues to confirm, that when it comes to [indiscernible], when it comes to PC or when it comes to automotive, the recovery is not what I think anyone had wished for. And that affect, I would say, a large part of our customer on all segments and application.

I think we also indeed mentioned as well some competitive dynamic on logic. I think that also has been express advance in the press in the last 3 months. I think that's not really new for you. And this also contributed to some of the pushout. So I think those 2 things are really the 2 dynamics that have come up in the last few months to a level where our customers basically started to really make, I would say, a decision that were in line with their expectations, both on the total market, but also maybe, in some cases, on the share they may end up having in some of the Logic market.

Source: Q3 2024 Earnings Call

This is further confirmed during the earnings call when Didier Scemama from BofA asked if the pushout is due to demand or customers struggle with technology. ASML CEO said that customers are making decision in line with their expectation “on the share they may end up having in some of the Logic market.”

In its preliminary Q3 preview, Samsung attached an apology letter. We might be seeing Samsung finally comes to term with the horrible state of its foundry process. Samsung could also be cutting some of the EUV orders for DRAM as its 1b nm process is unable to deliver the requirement needed for HBM3e qualification by Nvidia.

TSMC is increasingly becoming a monopoly at the advanced node for Logic

Capex today is capacity and market share in the future. If TSMC does not spent on 2nm capex in 2023, there will not be any 2nm revenue in 2025.

As I have written earlier in an article on Morris Chang’s 3 KPIs, capex today represents maximum potential market share in the future. Even if Intel’s 18A came to fruition, it will have limited market share without the necessary capacity. Customers have to believe that foundry have sufficient capacity for them before they choose to tape-out with the foundry.

Not only is Samsung losing its internal Exynos customer, but it is also increasingly likely that there will be partial outsourcing of Panther Lake tiles to TSMC in 2026 beyond Arrow and Lunar Lake. Panther Lake was supposed to showcase the success of 18A, but capex cut has happened, and Intel has become more active in its engagement with TSMC of late.

This is not TSMC gaining market share in foundry, but foundry gaining shares from the IDM. And at the advanced node, it looks like there is only 1 credible company remaining to drive the roadmap. This is not healthy for the industry in the long-term, but it was always meant to be with the economics of Moore’s Law

What does it mean for ASML if TSMC is increasingly becoming a bigger part of its EUV revenue? We have seen TSMC putting pricing pressure on ASML in its negotiation as TSMC recognised its dominant position in the industry. Lead time at ASML is also no longer as high as it used to be after capacity expansion.

When it comes to flexibility, I think there is some flexibility to the extent that orders would come in, in Q1. I think we'd still probably be able to cater to those orders in 2025. I think we build in sufficient flexibility to create that.

Source: Q3 2024 Earnings Call

In the near term, ASML will still have SK Hynix and Micron as they are ramping up their 1b nm and 1-gamma respectively. However, memory is cyclical in nature, and we are definitely nearer to the end of the semiconductor upcycle than the start of it.

EUV intensity is set to reduce in the next few years

ASML enjoyed higher share of WFE as EUV penetration rose rapidly from N7 to N3. However, the number of EUV layers is set to plateau as architecture changes such as GAA and Backside Power Delivery took place. The additional process steps will benefit mostly deposition and etching companies, especially for ASM International with its ALD and Epitaxy tool. TSMC has eliminated a couple of EUV layers from N3B to N3E. Number of EUV layer will be relatively flat at low 20s for N2 and A16 as TSMC relied on GAA and Super Power Rail respectively.

Eventually, the industry will still have to adopt High NA EUV as it further shrinks the transistor. This will happen nearer to the end of the decade, which is when ASML will start to gain share of WFE again as it did from 2018.

TSMC’s CoWoS capacity is in the focus after the acquisition of Innolux Tainan 4^th plant for NT$ 17 billion. The Innolux plant has been designated as AP8 which will become the 7^th advanced packaging plant of TSMC. Given the existing infrastructure, AP8 can start production in 2^nd half 2025 after some modification and equipment move-in. AP8 is significant as the total area is more than 96,000 sqm which is 9x larger than TSMC’s Zhunan AP6 plant.